SPRUJ28E November 2021 – September 2024 AM68 , AM68A , TDA4AL-Q1 , TDA4VE-Q1 , TDA4VL-Q1
The pixels (only RGB compontents) after the active matrix dithering unit are formatted on one or multiple cycles (from 1 to 3 cycles). On three cycles, two pixels can concatenate and send to the panel. The cycle format is selected through the DSS0_VP_CONTROL[24-23] TDMCYCLEFORMAT bit field. The number of bits for each cycle is set in the DSS0_VP_DATA_CYCLE_0 register for the first cycle, the DSS0_VP_DATA_CYCLE1 register for the second cycle, and the DSS0_VP_DATA_CYCLE2 register for the third cycle. The output interface data bus width, when TDM mode is enabled (DSS0_VP_CONTROL[20] TDMENABLE register bit = 1), can be 8, 9, 12, or 16 bits, configurable through the DSS0_VP_CONTROL[22-21] TDMPARALLELMODE register field.
When the TDM is disabled (DSS0_VP_CONTROL[20] TDMENABLE = 0), the video port output interface data bus width is configured through the DSS0_VP_CONTROL[10-8] DATALINES register field.
When using TDM mode, only up to 24 bits per pixel can be output on the interface. For higher color depth, only the upper bits are kept before converting each pixel into TDM output.
Figure 12-363 through Figure 12-366 show various examples of TDM settings in the function of pixel data formats and the interface data bus width.