SPRUJ28E November 2021 – September 2024 AM68 , AM68A , TDA4AL-Q1 , TDA4VE-Q1 , TDA4VL-Q1
The address fetch algorithm, TR and CR formats are defined in Transfer Request Record in DMA Architecture. It documents all features that can be supported by a Universal Transfer Controller (UTC) like the DRU but it may not support all of them. The DRU_CAPABILITIES register must be read to check what features of the TR are supported by the DRU.
The TR format allows to perform some kinds of data reformatting or to alter from the standard addressing formats. The DRU supports the transpose data reformatting function and the circular buffering alternate addressing algorithm.