SPRUJ28E November 2021 – September 2024 AM68 , AM68A , TDA4AL-Q1 , TDA4VE-Q1 , TDA4VL-Q1
The DSI receives all the clocks from DISPC or DPHY_TX modules. There are no other dedicated PLLs. For more details on DSI clocks mapping at DSS and SoC level, see DSI Integration.
The DSI requires multiple clocks running asynchronously, that are shown in Table 12-356.
Clock | Direction | Min | Max | Constraints | Description |
---|---|---|---|---|---|
dpi_0_clk (Async to all other clocks) | Input | 7 MHz | 425 MHz | Fpixel_clk = Ftx_byte_hs_clk × active_lanes × 8/(bits_per_pixel) | Used for DPI interface only. Frequency range depends on expected data rate with respect of number of data lanes, data lane frequency and frame rate |
sys_clk (Async to all other clocks) | Input | 7 MHz | 250 MHz | 1. Cannot be slower than tx_byte_hs_clk x datapath_size/if_datasize (risk of underrun) in SDI mode. 2. Must be greater than: rx_esc_clk x 8. 3. Speed should be sufficient to provide enough data in SDI operation. 4. Must be faster than the tx_byte_hs_clk for Direct command operation. | Main functional clock Also used for the VBUS/APB interface |
dphy_0_tx_byte_hs_clk (Async to all other clocks) | Input | 10 MHz | 312.5 MHz | The max value in SDI interface operation depends on sys_clk: can't exceed sys_clk freq x if_datasize datapath_size Otherwise 312.5 MHz to match the 2.5Gbps limit on DPHY v1.3 specification | DPHY PPI Byte Clock Frequency set by the DPHY and its High Speed input clock (tx_byte_hs_clk = dphy bit rate /8) Maximum limit due to risk of underrun |
dphy_0_tx_esc_clk (Async to all other clocks) | Input | 1 MHz | 20 MHz | No minimum limit is given by the DSI itself - while regular function mode max limit is 20 MHz | TX Escape Clock |
dphy_0_rx_esc_clk (Async to all other clocks) | Input | 1 MHz | 10 MHz | No minimum limit is given by the DSI itself - while regular function mode max limit is 10 MHz | RX Escape Clock |
Figure 12-378 describes the clock scheme and domains of the DSI_TX.