SPRUJ28E November 2021 – September 2024 AM68 , AM68A , TDA4AL-Q1 , TDA4VE-Q1 , TDA4VL-Q1
Table 6-70 lists the memory-mapped registers for the R5FSS_RAT. All register offset addresses not listed in Table 6-70 should be considered as reserved locations and the register contents should not be modified.
Offset | Acronym | Register Name | MCU_R5FSS_RAT_CFG Physical Address |
---|---|---|---|
0h | Section 3.2.14.1 | Revision register | 40F9 0000h |
4h | Section 3.2.14.2 | Config register | 40F9 0004h |
20h + formula | Section 3.2.14.3 | Region control register | 40F9 0020h + formula |
24h + formula | Section 3.2.14.4 | Region base register | 40F9 0024h + formula |
28h + formula | Section 3.2.14.5 | Region translated lower address register | 40F9 0028h + formula |
2Ch + formula | Section 3.2.14.6 | Region translated upper address register | 40F9 002Ch + formula |
804h | Section 3.2.14.7 | Destination ID register | 40F9 0804h |
820h | Section 3.2.14.8 | Exception logging control register | 40F9 0820h |
824h | Section 3.2.14.9 | Exception logging header 0 register | 40F9 0824h |
828h | Section 3.2.14.10 | Exception logging header 1 register | 40F9 0828h |
82Ch | Section 3.2.14.11 | Exception logging data 0 register | 40F9 082Ch |
830h | Section 3.2.14.12 | Exception logging data 1 register | 40F9 0830h |
834h | Section 3.2.14.13 | Exception logging data 2 register | 40F9 0834h |
838h | Section 3.2.14.14 | Exception logging data 3 register | 40F9 0838h |
840h | Section 3.2.14.15 | Exception logging interrupt pending set register | 40F9 0840h |
844h | Section 3.2.14.16 | Exception logging interrupt pending clear register | 40F9 0844h |
848h | Section 3.2.14.17 | Exception logging interrupt enable set register | 40F9 0848h |
84Ch | Section 3.2.14.18 | Exception logging interrupt enable clear register | 40F9 084Ch |
850h | Section 3.2.14.19 | EOI register | 40F9 0850h |
Offset | Acronym | Register Name | R5FSS_RAT_CFG Physical Address |
---|---|---|---|
0h | Section 3.2.14.1 | Revision register | 0FF9 0000h |
4h | Section 3.2.14.2 | Config register | 0FF9 0004h |
20h + formula | Section 3.2.14.3 | Region control register | 0FF9 0020h + formula |
24h + formula | Section 3.2.14.4 | Region base register | 0FF9 0024h + formula |
28h + formula | Section 3.2.14.5 | Region translated lower address register | 0FF9 0028h + formula |
2Ch + formula | Section 3.2.14.6 | Region translated upper address register | 0FF9 002Ch + formula |
804h | Section 3.2.14.7 | Destination ID register | 0FF9 0804h |
820h | Section 3.2.14.8 | Exception logging control register | 0FF9 0820h |
824h | Section 3.2.14.9 | Exception logging header 0 register | 0FF9 0824h |
828h | Section 3.2.14.10 | Exception logging header 1 register | 0FF9 0828h |
82Ch | Section 3.2.14.11 | Exception logging data 0 register | 0FF9 082Ch |
830h | Section 3.2.14.12 | Exception logging data 1 register | 0FF9 0830h |
834h | Section 3.2.14.13 | Exception logging data 2 register | 0FF9 0834h |
838h | Section 3.2.14.14 | Exception logging data 3 register | 0FF9 0838h |
840h | Section 3.2.14.15 | Exception logging interrupt pending set register | 0FF9 0840h |
844h | Section 3.2.14.16 | Exception logging interrupt pending clear register | 0FF9 0844h |
848h | Section 3.2.14.17 | Exception logging interrupt enable set register | 0FF9 0848h |
84Ch | Section 3.2.14.18 | Exception logging interrupt enable clear register | 0FF9 084Ch |
850h | Section 3.2.14.19 | EOI register | 0FF9 0850h |
R5FSS_RAT_PID is shown in Figure 6-26 and described in Table 6-73.
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This register contains the major and minor revisions for the module.
Instance | Physical Address |
---|---|
MCU_R5FSS_RAT_CFG | 40F9 0000h |
R5FSS_RAT_CFG | 0FF9 0000h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
REV | |||||||||||||||||||||||||||||||
R-66801100h | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | REV | R | 66801100h | TI internal data. Identifies revision of peripheral. |
R5FSS_RAT_CONFIG is shown in Figure 6-27 and described in Table 6-75.
Return to Summary Table.
This register contains the configuration values for the module.
Instance | Physical Address |
---|---|
MCU_R5FSS_RAT_CFG | 40F9 0004h |
R5FSS_RAT_CFG | 0FF9 0004h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | ADDR_WIDTH | ||||||||||||||
R-0h | R-30h | ||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ADDRS | REGIONS | ||||||||||||||
R-2h | R-10h | ||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-24 | RESERVED | R | 0h | Reserved. |
23-16 | ADDR_WIDTH | R | 30h | Number of address bits. |
15-8 | ADDRS | R | 2h | Number of addresses. |
7-0 | REGIONS | R | 10h | Number of regions. |
R5FSS_RAT_CTRL_j is shown in Figure 6-28 and described in Table 6-77.
Return to Summary Table.
This region controls the size and the enable for a region.
Offset = 20h + (j * 10h); where j = 0h to Fh.
Instance | Physical Address |
---|---|
MCU_R5FSS_RAT_CFG | 40F9 0020h + formula |
R5FSS_RAT_CFG | 0FF9 0020h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
EN | RESERVED | ||||||||||||||
R/W-0h | R-0h | ||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SIZE | ||||||||||||||
R-0h | R/W-0h | ||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | EN | R/W | 0h | Enable for the region. |
30-6 | RESERVED | R | 0h | Reserved. |
5-0 | SIZE | R/W | 0h | Size of the region in address bits. |
R5FSS_RAT_BASE_j is shown in Figure 6-29 and described in Table 6-79.
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This register is used for the base address for a region. This is the source address for matching to a region.
Offset = 24h + (j * 10h); where j = 0h to Fh.
Instance | Physical Address |
---|---|
MCU_R5FSS_RAT_CFG | 40F9 0024h + formula |
R5FSS_RAT_CFG | 0FF9 0024h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
BASE | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | BASE | R/W | 0h | Base address for the region. It must be aligned to the programmed size. |
R5FSS_RAT_TRANS_L_j is shown in Figure 6-30 and described in Table 6-81.
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This register contains the translated lower address bits for a region.
Offset = 28h + (j * 10h); where j = 0h to Fh.
Instance | Physical Address |
---|---|
MCU_R5FSS_RAT_CFG | 40F9 0028h + formula |
R5FSS_RAT_CFG | 0FF9 0028h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
LOWER | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | LOWER | R/W | 0h | Translated lower address bits for the region. It must be aligned to the programmed size. |
R5FSS_RAT_TRANS_U_j is shown in Figure 6-31 and described in Table 6-83.
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This register contains the translated upper address bits for a region.
Offset = 2Ch + (j * 10h); where j = 0h to Fh
Instance | Physical Address |
---|---|
MCU_R5FSS_RAT_CFG | 40F9 002Ch + formula |
R5FSS_RAT_CFG | 0FF9 002Ch + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | UPPER | ||||||||||||||||||||||||||||||
R-0h | R/W-0h | ||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved. |
15-0 | UPPER | R/W | 0h | Translated upper address bits for the region. |
R5FSS_RAT_DESTINATION_ID is shown in Figure 6-32 and described in Table 6-85.
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This register defines the destination ID value for error messages.
Instance | Physical Address |
---|---|
MCU_R5FSS_RAT_CFG | 40F9 0804h |
R5FSS_RAT_CFG | 0FF9 0804h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | DEST_ID | ||||||||||||||||||||||||||||||
R-0h | R/W-0h | ||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved. |
7-0 | DEST_ID | R/W | 0h | Destination ID. |
R5FSS_RAT_EXCEPTION_LOGGING_CONTROL is shown in Figure 6-33 and described in Table 6-87.
Return to Summary Table.
This register controls the exception logging.
Instance | Physical Address |
---|---|
MCU_R5FSS_RAT_CFG | 40F9 0820h |
R5FSS_RAT_CFG | 0FF9 0820h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | DISABLE_INTR | DISABLE_F | |||||
R-0h | R/W-0h | R/W-0h | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-2 | RESERVED | R | 0h | Reserved. |
1 | DISABLE_INTR | R/W | 0h | Disables logging interrupt when set. |
0 | DISABLE_F | R/W | 0h | Disables logging when set. |
R5FSS_RAT_EXCEPTION_LOGGING_HEADER0 is shown in Figure 6-34 and described in Table 6-89.
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This register contains the first word of the header.
Instance | Physical Address |
---|---|
MCU_R5FSS_RAT_CFG | 40F9 0824h |
R5FSS_RAT_CFG | 0FF9 0824h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TYPE_F | SRC_ID | DEST_ID | |||||||||||||||||||||||||||||
R-0h | R-0h | R-0h | |||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-24 | TYPE_F | R | 0h | Type. |
23-8 | SRC_ID | R | 0h | Source ID. |
7-0 | DEST_ID | R | 0h | Destination ID. |
R5FSS_RAT_EXCEPTION_LOGGING_HEADER1 is shown in Figure 6-35 and described in Table 6-91.
Return to Summary Table.
This register contains the second word of the header.
Instance | Physical Address |
---|---|
MCU_R5FSS_RAT_CFG | 40F9 0828h |
R5FSS_RAT_CFG | 0FF9 0828h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
GROUP | CODE | RESERVED | |||||||||||||||||||||||||||||
R-0h | R-0h | R-0h | |||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-24 | GROUP | R | 0h | Group. |
23-16 | CODE | R | 0h | Code. |
15-0 | RESERVED | R | 0h | Reserved. |
R5FSS_RAT_EXCEPTION_LOGGING_DATA0 is shown in Figure 6-36 and described in Table 6-93.
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This register contains the first word of the data.
Instance | Physical Address |
---|---|
MCU_R5FSS_RAT_CFG | 40F9 082Ch |
R5FSS_RAT_CFG | 0FF9 082Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ADDR_L | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | ADDR_L | R | 0h | Address lower 32 bits. |
R5FSS_RAT_EXCEPTION_LOGGING_DATA1 is shown in Figure 6-37 and described in Table 6-95.
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This register contains the second word of the data.
Instance | Physical Address |
---|---|
MCU_R5FSS_RAT_CFG | 40F9 0830h |
R5FSS_RAT_CFG | 0FF9 0830h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | ADDR_H | ||||||||||||||||||||||||||||||
R-0h | R-0h | ||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved. |
15-0 | ADDR_H | R | 0h | Address upper 12 bits. |
R5FSS_RAT_EXCEPTION_LOGGING_DATA2 is shown in Figure 6-38 and described in Table 6-97.
Return to Summary Table.
This register contains the third word of the data.
Instance | Physical Address |
---|---|
MCU_R5FSS_RAT_CFG | 40F9 0834h |
R5FSS_RAT_CFG | 0FF9 0834h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | ROUTEID | ||||||
R-0h | R-0h | ||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
ROUTEID | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | WRITE | READ | DEBUG | CACHEABLE | PRIV | SECURE | |
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PRIV_ID | |||||||
R-0h | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-28 | RESERVED | R | 0h | Reserved. |
27-16 | ROUTEID | R | 0h | Route ID. |
15-14 | RESERVED | R | 0h | Reserved. |
13 | WRITE | R | 0h | Write. |
12 | READ | R | 0h | Read. |
11 | DEBUG | R | 0h | Debug. |
10 | CACHEABLE | R | 0h | Cacheable. |
9 | PRIV | R | 0h | Priv. |
8 | SECURE | R | 0h | Secure. |
7-0 | PRIV_ID | R | 0h | Priv ID. |
R5FSS_RAT_EXCEPTION_LOGGING_DATA3 is shown in Figure 6-39 and described in Table 6-99.
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This register contains the fourth word of the data. Reading this register will clear the error pending bit.
Instance | Physical Address |
---|---|
MCU_R5FSS_RAT_CFG | 40F9 0838h |
R5FSS_RAT_CFG | 0FF9 0838h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | BYTECNT | ||||||||||||||||||||||||||||||
R-0h | R-0h | ||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-10 | RESERVED | R | 0h | Reserved. |
9-0 | BYTECNT | R | 0h | Byte count. |
R5FSS_RAT_EXCEPTION_PEND_SET is shown in Figure 6-40 and described in Table 6-101.
Return to Summary Table.
This register allows to set the exception pending signal.
Instance | Physical Address |
---|---|
MCU_R5FSS_RAT_CFG | 40F9 0840h |
R5FSS_RAT_CFG | 0FF9 0840h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | PEND_SET | ||||||
R-0h | R/W1S-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R | 0h | Reserved. |
0 | PEND_SET | R/W1S | 0h | Write a 1 to set the exception pending signal. |
R5FSS_RAT_EXCEPTION_PEND_CLEAR is shown in Figure 6-41 and described in Table 6-103.
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This register allows to clear the pend signal.
Instance | Physical Address |
---|---|
MCU_R5FSS_RAT_CFG | 40F9 0844h |
R5FSS_RAT_CFG | 0FF9 0844h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | PEND_CLR | ||||||
R-0h | R/W1C-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R | 0h | Reserved. |
0 | PEND_CLR | R/W1C | 0h | Write a 1 to clear the exception pending signal. |
R5FSS_RAT_EXCEPTION_ENABLE_SET is shown in Figure 6-42 and described in Table 6-105.
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This register allows to set the interrupt enable signal.
Instance | Physical Address |
---|---|
MCU_R5FSS_RAT_CFG | 40F9 0848h |
R5FSS_RAT_CFG | 0FF9 0848h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | ENABLE_SET | ||||||
R-0h | R/W1S-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R | 0h | Reserved. |
0 | ENABLE_SET | R/W1S | 0h | Write a 1 to set the exception interrupt enable signal. |
R5FSS_RAT_EXCEPTION_ENABLE_CLEAR is shown in Figure 6-43 and described in Table 6-107.
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This register allows to clear the interrupt enable signal.
Instance | Physical Address |
---|---|
MCU_R5FSS_RAT_CFG | 40F9 084Ch |
R5FSS_RAT_CFG | 0FF9 084Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | ENABLE_CLR | ||||||
R-0h | R/W1C-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R | 0h | Reserved. |
0 | ENABLE_CLR | R/W1C | 0h | Write a 1 to clear the exception interrupt enable signal. |
R5FSS_RAT_EOI_REG is shown in Figure 6-44 and described in Table 6-109.
Return to Summary Table.
EOI Register.
The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt handler must write to the EOI register at the end of the current interrupt processing routine, so that new events can re-trigger the pulse interrupt signal again. For level interrupt signals the EOI register is not functional and must not be used.
Instance | Physical Address |
---|---|
MCU_R5FSS_RAT_CFG | 40F9 0850h |
R5FSS_RAT_CFG | 0FF9 0850h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | EOI_WR | ||||||||||||||||||||||||||||||
R-0h | R/W-0h | ||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved. |
15-0 | EOI_WR | R/W | 0h | EOI value. |