SPRUJ28E November 2021 – September 2024 AM68 , AM68A , TDA4AL-Q1 , TDA4VE-Q1 , TDA4VL-Q1
Each PLL in MAIN domain has a dedicated register CTRLMMR_WKUP_MAIN_PLLn_CLKSEL in WKUP_CTRL_MMR0 to choose its reference clock.
MAIN_PLLn_REF_CLK (n = 0 to 8, 12 to 19, 23 to 25) clock source is selected by means of CTRLMMR_WKUP_MAIN_PLLn_CLKSEL[0] CLK_SEL bit; for more information about control registers, see Control Module (CTRL_MMR). The encoding of CLK_SEL is shown in Table 5-40.
CTRLMMR_WKUP_MAIN_PLLn_CLKSEL(1)[0] CLK_SEL | MAIN_PLLn_ REF_CLK Selection (1) |
---|---|
0 (default) | WKUP_HFOSC0_CLK |
1 | HFOSC1_CLK |
PLL4 (AUDIO0 PLL) input reference clocks have additional selection via mux configured in the CTRLMMR_WKUP_MAIN_PLL4_CLKSEL[4] XREF_SEL in WKUP_CTRL_MMR0 (see Table 5-41); for more information about control registers, see Control Module (CTRL_MMR).
CTRLMMR_WKUP_MAIN_PLL4_CLKSEL[4] XREF_SEL | PLL4 (AUDIO0 PLL) Ref Selection |
---|---|
0 (default) | MAIN_PLL4_REF_CLK already selected via MAIN_PLL4_REF_CLK[0] CLK_SEL |
1 | EXT_REFCLK1 (external clock input on device pins) |