The device provides several system clock outputs.
Summary of these output clock signals is as follows:
- MCU_CLKOUT0
- Reference clock
output for Ethernet PHYs (50 MHz or 25 MHz)
- MCU_SYSCLKOUT0
- MCU_SYSCLK0 is
divided by 4 and then sent out of the device as a LVCMOS clock
signal (MCU_SYSCLKOUT0). This signal can be used to test if the main
chip clock is functioning or not. This signal should not be used as
a clock source for external devices on a board.
- MCU_OBSCLK0
- On the clock output
MCU_OBSCLK0, oscillators and PLLs clocks can be observed for tests
and debug. This signal should not be used as a clock source for
external devices on a board.
- SYSCLKOUT0
- SYSCLK0 is divided by
4 and then sent out of the device as a LVCMOS clock signal
(SYSCLKOUT0). This signal can be used to test if the main chip clock
is functioning or not. This signal should not be used as a clock
source for external devices on a board.
- CLKOUT
- Reference clock
output for Ethernet PHYs (50 MHz)
- OBSCLK[1:0]
- On the clock output
OBSCLK0/1, oscillators and PLLs clocks can be observed for tests and
debug.
Other clock outputs, that are routed directly from subsystems to device pins, are described in the respective module chapter.
Observation clock pins - MCU_OBSCLK0, OBSCLK0, OBSCLK1, and OBSCLK2 serve the following purposes:
- During testing, PLLs on the device are configured to output all operating frequencies desired by each module to characterize PLL performance.
- System debug: during debug, clocks from various PLLs can be inspected for possible clues. Example clock glitches, lock loss etc.
Note: Maximum frequency supported on both MCU_OBSCLK0, OBSCLK0, OBSCLK1, and OBSCLK2 pins is 200 MHz. Hence the divider at the output of each OBSCLK mux must be programmed to meet this limitation.
Unlike the OBSCLK pins which can select several different clocks for output, system clock pins (MCU_SYSCLKOUT0 and SYSCLKOUT0) are hardwired to dedicated clock resources (see Section 5.4.5.2)