SPRUJ28E November 2021 – September 2024 AM68 , AM68A , TDA4AL-Q1 , TDA4VE-Q1 , TDA4VL-Q1
ROM code must be aware of the reference clock provided to PLLs. That is, the speed of the quartz crystal, or the clock supplied by an external clock oscillator. On how to indicate the PLL reference clock, see Table 4-3, PLL Reference Clock Selection.
See Clock Management, for the PLL reference clock scheme.
ROM code configures only PLLs which are required during boot. Therefore, if a PLL is required for the backup boot mode but not the primary boot mode, and if the backup boot mode never executes, then the PLLs required for backup boot are not enabled. Table 4-49 lists the enabled PLLs according to module or boot peripheral.
MCU_PLL0 | MCU_PLL1 | MCU_PLL2 | Main PLL0 | Main PLL1 | Main PLL2 | Main PLL3 | Boot Mode |
---|---|---|---|---|---|---|---|
✓ | ✓ | Hyperflash | |||||
✓ | ✓ | OSPI/QSPI/SPI | |||||
✓ | ✓ | Ethernet | |||||
✓ | ✓ | I2C | |||||
✓ | ✓ | UART | |||||
✓ | ✓ | eMMC/MMC/SD | |||||
✓ | ✓ | ✓ | USB | ||||
✓ | ✓ | ✓ | PCIe | ||||
✓ | Serial NAND |
All clock frequencies are in megahertz.