SPRUJ28E November 2021 – September 2024 AM68 , AM68A , TDA4AL-Q1 , TDA4VE-Q1 , TDA4VL-Q1
CA bits can be swizzled between any bit positions via the DDRSS_PHY_1053[23-0] PHY_ADR_ADDR_SEL_0 field.
When the memory subsystem consists of more than one LPDDR device on the full bus width (two 16 bit devices on a 32 bit bus), all devices receive the same CA bits at some timing relative to each other depending on board placement and routing. In these cases, the DDR PHY can only supply a single CA training value for all devices to use together. Since each device may not receive ideal timing, the CA timing margin is reduced in the overall memory subsystem. Either a single one (any of them) or any combination of the devices participating in the training can be individually selected via the DDRSS_PHY_1357[20-16] PHY_CALVL_DEVICE_MAP field.
In case of two channels, each one can be assigned to a specific chip select and data slices. The DDRSS_PHY_1293[31-24] PHY_CALVL_CS_MAP field is used to map each CS rank to the appropriate DQ slice for training data return.
Bit 1 of the DDRSS_PHY_1038[25-24] PHY_ADR_CALVL_RANK_CTRL_0 field enables current training results to be taken into account along with new training results, instead of discarding previous results. This can be used to train each rank or channel and construct an aggregate for all of them. Each rank or channel then receives the same CA training timing that is the best case possible for all of them. This may result in the setup/hold margin for the CA bits being narrower than any single rank or channel could achieve by itself.
When multiple frequency sets are supported, then all ranks for a given frequency set must be trained before changing to a new frequency. Failure to do so results in rank aggregation not being performed completely with possible data corruption due to rank training being improper.
In case of multiple channels each rank of a channel must use the same CA swizzle. Each rank of a channel must also use the same DQ swizzle.
If the memory device DQ bits are not received in the same order at the PHY as the LPDDR device sent them, then the DQ data has been swizzled, and must be reordered back to its original form before CA training can interpret the results. The following fields specify the DQ swizzling in the corresponding data slice:
The PHY_DQ_DM_SWIZZLE0_x fields contain the bit position to map the received read DQ bits for proper comparison with the training pattern bits.
After CA training is complete the DDRSS_PHY_1043[31-0] PHY_ADR_CALVL_OBS1_0 field can be read to obtain training status information.
After CA training is complete, software can always override the results by writing to the following fields:
The PHY_ADRx_CLK_WR_SLAVE_DELAY_0 fields can be programmed between 0x000 and 0x600. While training is permitted to set these fields below 0x0C0, the final result is always greater than 0x0C0. If software overrides training results, values less than 0x0C0 should never be programmed. The same restriction applies also to the PHY_GRPy_SLAVE_DELAY_x fields.