SPRUJ28E November 2021 – September 2024 AM68 , AM68A , TDA4AL-Q1 , TDA4VE-Q1 , TDA4VL-Q1
The Private Read message transmitted over I3C bus in all supported transmit modes is presented in Figure 12-26, Master Read Transaction for Single and Multi Address Sequences
Similarly to Private Write message, each I3C read frame is preceded by I3C write frame which sends slave register address to be read. After sending the command, firmware should wait for I3C_MST_ISR[16] IMM_COMP interrupt which signals the end of message and RX FIFO content ready to read.
In case of payload lengths exceeding RX FIFO size, firmware should utilize I3C_MST_ISR[7] TX_THR interrupt to read RX FIFO before it gets filled and prevent from data corruption. For easier management of long FIFO and/or long host read intervals, the amount of data available in FIFO that triggers the interrupt can be programmed according to actual conditions in given system.