SPRUJ28E November 2021 – September 2024 AM68 , AM68A , TDA4AL-Q1 , TDA4VE-Q1 , TDA4VL-Q1
This section describes module ports related to clocks, resets, and hardware requests.
Clocks | |
Module Clock Input | Description |
MCSPI_ICLK | MCSPI Interface Clock |
MCSPI_FCLK | MCSPI Functional Clock |
Resets | |
Module Reset Input | Description |
MCSPI_RST | MCSPI Asynchronous Reset |
MCSPI_POR_RST | MCSPI Power-On Reset |
Interrupt Requests | ||
Module Interrupt Signal | Description | Type |
MCSPI_INTR_SPI_0 | MCSPI Interrupt Request | Level |
DMA Events | ||
Module DMA Event | Description | Type |
MCSPI_DMA_WRITE_EVENT0 | MCSPI Channel 0 Transmit (Write) Request Line | Pulse |
MCSPI_DMA_READ_EVENT0 | MCSPI Channel 0 Receive (Read) Request Line | Pulse |
MCSPI_DMA_WRITE_EVENT1 | MCSPI Channel 1 Transmit (Write) Request Line | Pulse |
MCSPI_DMA_READ_EVENT1 | MCSPI Channel 1 Receive (Read) Request Line | Pulse |
MCSPI_DMA_WRITE_EVENT2 | MCSPI Channel 2 Transmit (Write) Request Line | Pulse |
MCSPI_DMA_READ_EVENT2 | MCSPI Channel 2 Receive (Read) Request Line | Pulse |
MCSPI_DMA_WRITE_EVENT3 | MCSPI Channel 3 Transmit (Write) Request Line | Pulse |
MCSPI_DMA_READ_EVENT3 | MCSPI Channel 3 Receive (Read) Request Line | Pulse |