SPRUJ28E November 2021 – September 2024 AM68 , AM68A , TDA4AL-Q1 , TDA4VE-Q1 , TDA4VL-Q1
The MSMC2DDR bridge checks the VBUSM.C address received against the valid SDRAM address space programmed in the DDRSS_V2A_CTL_REG register. If the VBUSM.C address for an access falls outside the programmed range the bridge sets to 0x1 the DDRSS_V2A_INT_RAW_REG[1] AERR bit and also triggers the DDR0_DDRSS_V2A_OTHER_ERR_LVL_0 interrupt. The address and the Route ID for the command caused error are logged in the DDRSS_V2A_AERR_LOG1_REG and DDRSS_V2A_AERR_LOG2_REG registers.
The valid address range can be programmed using the DDRSS_V2A_CTL_REG[9-5] SDRAM_IDX and DDRSS_V2A_CTL_REG[4-0] REGION_IDX fields. Table 8-15 summarizes the scenarios for determining valid address range and interrupt generation.
| Condition | Description |
|---|---|
| REGION_IDX = SDRAM_IDX | DDR region size is equal to the connected SDRAM size. It is SoC responsibility to ensure that the addresses received by the DDR subsystem do not fall outside the region size. No address error is generated if the address received falls outside the region size. |
| REGION_IDX < SDRAM_IDX | DDR region size is less than the connected SDRAM size. It is SoC responsibility to ensure that the addresses received by the DDR subsystem do not fall outside the region size. No address error is generated if the address received falls outside the region size. |
| REGION_IDX > SDRAM_IDX | DDR region size is greater than the connected SDRAM size. Address error is generated if the address received falls outside the connected SDRAM size. |
A write access outside the programmed range is discarded. A write error associated status is sent back to the VBUSM.C interface.
A read access outside the programmed range is executed on the SDRAM interface as a normal read, but data will contain all zeroes before forwarding it to the VBUSM.C interface. A read error associated status is sent back to the VBUSM.C interface along with the read data containing all zeroes.
When inline ECC is enabled, the available SDRAM size is reduced by 1/9th of the size programmed in the SDRAM_IDX field. Therefore, the bridge reports an error if an access falls outside the reduced SDRAM size when inline ECC is enabled. The reduced SDRAM size limit applies to all accesses, both to the protected and non-protected ECC regions.