SPRUJ28E November 2021 – September 2024 AM68 , AM68A , TDA4AL-Q1 , TDA4VE-Q1 , TDA4VL-Q1
Figure 12-167 shows an example of continuous capture operation (Mod4 counter wraps around). In this figure, TSCTR counts-up without resetting and capture events are qualified on the rising edge only, this gives period (and frequency) information.
On an event, the TSCTR contents (time-stamp) is first captured, then Mod4 counter is incremented to the next state. When the TSCTR reaches FFFF FFFFh (maximum value), it wraps around to 0000 0000h (not shown in Figure 12-167), if this occurs, the CNTOVF_FLG (counter overflow) flag is set, and an interrupt (if enabled) occurs. Captured time-stamps are valid at the point indicated by the diagram, after the 4-th event, hence event CEVT4 can conveniently be used to trigger an interrupt and the CPU can read data from the CAPn registers.
Register | Bit | Value |
---|---|---|
ECCTL1 | CAP1POL | EC_RISING |
ECCTL1 | CAP2POL | EC_RISING |
ECCTL1 | CAP3POL | EC_RISING |
ECCTL1 | CAP4POL | EC_RISING |
ECCTL1 | CTRRST1 | EC_ABS_MODE |
ECCTL1 | CTRRST2 | EC_ABS_MODE |
ECCTL1 | CTRRST3 | EC_ABS_MODE |
ECCTL1 | CTRRST4 | EC_ABS_MODE |
ECCTL1 | CAPLDEN | EC_ENABLE |
ECCTL1 | PRESCALE | EC_DIV1 |
ECCTL2 | CAP_APWM | EC_CAP_MODE |
ECCTL2 | CONT_ONESHT | EC_CONTINUOUS |
ECCTL2 | SYNCO_SEL | EC_SYNCO_DIS |
ECCTL2 | SYNCI_EN | EC_DISABLE |
ECCTL2 | TSCTRSTOP | EC_RUN |