SPRUJ28E November 2021 – September 2024 AM68 , AM68A , TDA4AL-Q1 , TDA4VE-Q1 , TDA4VL-Q1
Figure 12-153 and Table 12-227 show a Command Queuing initialization sequence.
Step | Description |
---|---|
1 | Initialize and enable Command Queueing in the device. |
2 | Configure Task Descriptor size in MMCSD0_CQ_CONFIG register. |
3 | Configure MMCSD0_CQ_TDL_BASE_ADDR and MMCSD0_CQ_TDL_BASE_ADDR_UPBITS registers to point to the memory location allocated to the TDL in host memory. |
4 | Configure CQSST and CQSSBC to control when SEND_QUEUE_STATUS commands are sent to the device by CQE. |
5 | Configure MMCSD0_CQ_INTR_COALESCING register to control the interrupt coalescing feature: enable/disable, set interrupt count and timer protection. |
6 | Configure MMCSD0_CQ_RESP_ERR_MASK register to control which errors may trigger a RED interrupt (if different from reset values). |
7 | Write '1' to MMCSD0_CQ_CONFIG register to enable CQE activity. |