SPRUJ28E November 2021 – September 2024 AM68 , AM68A , TDA4AL-Q1 , TDA4VE-Q1 , TDA4VL-Q1
This section describes SerDes module ports related to clocks, resets, and hardware requests.
Clocks | |
Module Clock Input | Description |
SERDES_ICLK | VBUS interface clock |
CMN_REFCLK_INT | Internal reference clock from device sources. Software selectable. |
Resets | |
Module Reset Input | Description |
SERDES_RST | Serdes LPSC reset |
Interrupt Requests | ||
Module Interrupt Signal | Description | Type |
PHY_PWR_TIMEOUT_LVL_0 | Lane power timeout interrupt | Level |
DMA Events | ||
Module DMA Event | Description | Type |
- | No PDMA channels to external DMA engines | - |