SPRUJ28E November 2021 – September 2024 AM68 , AM68A , TDA4AL-Q1 , TDA4VE-Q1 , TDA4VL-Q1
To verify the eMMC5.1 PHY functionality, the BIST function is built on top of the eMMC5.1 PHY that can either be controlled from SOC registers or from special Vendor Registers defined in the TI's eMMC5.1 Host Controller. The functionality of the BIST is to be able to test various functions of the PHY (without using the eMMC protocol/software stack) and provide the results of the testing to the diagnostic software.
The BIST logic drives a known pattern on the transmit path (into DFE) and is received on the receive path (as the IOs are bidirectional in nature). The received data is captured in the BIST logic (after the DFE) and are compared. The result of the pattern comparision is reported into status register for software to read out.
The fixed pattern is the well-known tuning pattern used in HS200 mode as defined by the JEDEC. This pattern is 128-bytes in length, is preceded by eMMC START Condition on all lanes, and is terminated with END Condition on all lanes. Unlike the normal Tuning command, there is no CRC appended to this pattern.
The 128-byte Test Pattern is as follows:
In non-HS200 Modes, the testing is performed for one time with programmed Tx Phase and Rx Phase values. In HS200 Mode, the testing is performed 32-times and it is expected that some of the iterations will have data mismatch because of the RxPhase Timing. The BIST engine iterates through all 32-phases of Rx Clock and provides the result of data/cmd line compare for each of the phases in a 32-bit status vector.