SPRUJ28E November 2021 – September 2024 AM68 , AM68A , TDA4AL-Q1 , TDA4VE-Q1 , TDA4VL-Q1
Once the non-realtime channel configuration has been done the DRU_CHRT_CTL_j[31] ENABLE bit should be written. It must be written before any TRs can be written. The mechanism to write this bit is based on the ownership of the channel as specified via the DRU_CFG_j[19] CHAN_TYPE_OWNER bit. If the owner is a CPU, than this bit must be written directly through the DRU configuration interface. If the owner is UDMA, than the PSI-L interface must be used to write the ENABLE bit through the PSI-L register configuration write process as described in PSI-L.
Once a channel has been enabled the channel configuration registers cannot be modified. The channel can only be disabled through writing 0x1 to the DRU_CHRT_CTL_j[30] TEARDOWN bit.