SPRUJ28E November 2021 – September 2024 AM68 , AM68A , TDA4AL-Q1 , TDA4VE-Q1 , TDA4VL-Q1
The prefetch mode is selected when the GPMC_PREFETCH_CONFIG1[0] ACCESSMODE bit is cleared.
The NAND software driver must issue the block and page opening (READ) command with the correct data address pointer initialization before the engine can be started to read from the NAND memory device. The engine is started by asserting the GPMC_PREFETCH_CONTROL[0] STARTENGINE bit. The STARTENGINE bit automatically clears when the prefetch process completes.
If required, the ECC calculator engine must be initialized (that is, reset, configured, and enabled) before the prefetch engine is started so that the ECC is computed correctly on all data read by the prefetch engine.
When the GPMC_PREFETCH_CONFIG1[3] SYNCHROMODE bit is cleared, the prefetch engine starts requesting data as soon as the STARTENGINE bit is set. If using this configuration, the host must monitor the NAND device-ready pin so that it sets the STARTENGINE bit only when the NAND device is in a ready state (that is, data is valid for prefetching).
When the SYNCHROMODE bit is set, the prefetch engine starts requesting data when an active-to-inactive WAIT signal transition is detected. The transition detector must be cleared before any transition detection (see Section 12.3.4.3.11.2.2, Ready Pin Monitored by Hardware Interrupt). The GPMC_PREFETCH_CONFIG1[5-4] WAITPINSELECTOR bit field selects which GPMC_WAIT pin edge detector triggers the prefetch engine in this synchronized mode.
If the STARTENGINE bit is set after the NAND address phase (page opening command), the engine is effectively started only after the actual NAND address phase completion. To prevent GPMC stall during this NAND address phase, set the STARTENGINE bit before NAND address phase completion when in synchronized mode. The prefetch engine starts when an active-to-inactive WAIT signal transition is detected. The STARTENGINE bit is automatically cleared on prefetch process completion.
The prefetch engine issues a read request to fill the FIFO with the amount of data specified by the GPMC_PREFETCH_CONFIG2[13-0] TRANSFERCOUNT bit field.
Table 12-178 describes the prefetch mode configuration.
Bit Field | Register | Value | Comments |
---|---|---|---|
STARTENGINE | GPMC_PREFETCH_CONTROL[0] | 0 | Prefetch engine can be configured only if STARTENGINE is set to 0. |
ENGINECSSELECTOR | GPMC_PREFETCH_CONFIG1[26-24] | 0 to 3 | Selects the chip-select associated with a NAND device where the prefetch engine is active. |
ACCESSMODE | GPMC_PREFETCH_CONFIG1[0] | 0 | Selects prefetch mode |
FIFOTHRESHOLD | GPMC_PREFETCH_CONFIG1[14-8] | Selects the maximum number of bytes read or written by the host on DMA or interrupt request | |
TRANSFERCOUNT | GPMC_PREFETCH_CONFIG2[13-0] | Selects the number of bytes to be read or written by the engine to the selected chip-select | |
SYNCHROMODE | GPMC_PREFETCH_CONFIG1[3] | 0/1 | Selects when the engine starts the access to the chip-select |
WAITPINSELECT | GPMC_PREFETCH_CONFIG1[17-16] | 0 to 1 | Selects WAIT pin edge detector (if GPMC_PREFETCH_CONFIG1[3] SYNCHROMODE = 0x1) |
ENABLEOPTIMIZEDACCESS | GPMC_PREFETCH_CONFIG1[27] | 0/1 | See Section 12.3.4.3.11.4.6, Optimizing NAND Access Using the Prefetch and Write-Posting Engine. |
CYCLEOPTIMIZATION | GPMC_PREFETCH_CONFIG1[30-28] | Number of clock cycle removed to timing parameters | |
ENABLEENGINE | GPMC_PREFETCH_CONFIG1[7] | 1 | Engine enabled |
STARTENGINE | GPMC_PREFETCH_CONTROL[0] | 1 | Starts the prefetch engine |