SPRUJ28 User guide

SPRUJ28E November 2021 – September 2024 AM68 , AM68A , TDA4AL-Q1 , TDA4VE-Q1 , TDA4VL-Q1

5.5.17.2 GPU Integration Details

GPU Firmware Processor General Purpose Interface Details

The Firmware Processor General Purpose Interface of the GPU allows for messages to be passed between the GPU and another processor Core on the SoC. The interface consists of two channels:

Firmware Processor Transmit (Output) Channel
- Data (8 bits) provided by GPU to another CPU on the SOC
- Data transfers are initiated by the GPU asserting gpio_tx_req
- Receipt of Data is Acknowledged by the other CPU asserting gpio_tx_ack
- When the GPU receives the Acknowledge from the other CPU, it deasserts gpio_tx_req
- When the other CPU sees gpio_tx_req deasserted, it deasserts gpio_tx_ack
Firmware Processor Receive (Input) Channel
- Data (8 bits) provided by another CPU to the GPU
- Data transfers are initiated by the other CPU asserting gpio_rx_req
- Receipt of Data is Acknowledged by the GPU asserting gpio_rx_ack

On J7AEP and J7AHP, the GPU's general purpose interface is exposed to each of the SoC CPUs through CTRLMMR0 registers with interrupt signaling in each direction:

GPU Firmware Transmit (output) Channel Operation

The GPU Transmit Channel allows the GPU firmware processor to send data to an external CPU on the SoC. It operates as follows (see diagram):

When the GPU Firmware Processor enters the 'send' state, it begins by driving gpio_tx_data[7:0] with valid data ('data1') and driving gpio_tx_req active. The GPU will drive these signals in the same GPU clock cycle. The firmware then transitions to the wait_ack state where it remains until it sees gpio_tx_ack asserted.
Assertion of the gpio_tx_rq signal while gpio_tx_ack is low causes an interrupt request on gpu_gpio_reqint.
One of the other CPUs on the SoC responds to the interrupt by entering an ISR
As a result of the interrupt (shown here as within the ISR, but not required to be) the CPU reads from the GPU_GP_OUT_REQ register in the CTRL_MMR0 module. The read returns the output data and the active state of the gpio_tx_req signal.
After reading the transmitted data, the CPU writes to the GPU_GP_OUT_ACK register to set the ack bit.
Setting GPU_GP_OUT_ACK_ack bit causes the gpio_tx_ack signal to be asserted.
The interrupt gpu_gpio_reqint interrupt is cleared by the assertion of gpio_tx_ack.
The GPU Firmware processor enters the ‘end’ state to terminate the transaction.
The GPU Firmware processor terminates the transaction by de-asserting gpio_tx_req. Valid data is no longer required to be output on gpio_tx_data[7:0]
The gpio_tx-req de-assertion resets the CTRL_MMR0 GPU_GP_OUT_ACK_ack bit and clears the GPU_GP_OUR_REQ_req bit.
The GPU_GP_OUT_ACK_ack bit reset de-asserts the gpio_tx_ack signal completing the handshake and returning the GPU GPIO to the idle state from which a new transfer may begin.

GPU Firmware Receive (Input) Channel Operation

The GPU Receive Channel allows an external CPU on the SoC to send data to the GPU firmware processor. It operates as follows (see diagram):

The CPU must poll the GPU_GP_IN_ACK.ack bit for ‘0’ at the beginning of the send operation, to ensure that the GPU has released the gpio_rx_ack signal. If this step is skipped and the GPU still has gpio_rx_ack asserted, then a gpu_rx_ackint interrupt will be sent to the CPU immediately before the GPU has read the GPIO data.
After verifying that gpio_rx_ack is de-asserted the CPU may continue the GPIO send process.
The CPU writes the send data in GPU_GP_IN_REQ_data[7:0] bits and sets the GPU_GP_IN_REQ_req bit.
The setting of the GPU_GP_IN_REQ.req bit causes the gpio_rx_req GPU input to be asserted.
The GPU Firmware processor sees gpio_rx_req asserted and enters the GPIO receive state.
The GPU Firmware processor reads the valid data from the gpio_rx_data[7:0] inputs
The GPU Firmware processor enters the GPIO ack state
The GPU Firmware processor acknowledges data read completion by asserting gpio_rx_ack which sets the GPU_GP_IN_ACK.ack bit.
The assertion of both gpio_rx_req and gpio_rx_ack activates the gpu_gpio_ackint interrupt
The enabled interrupt causes the CPU to enter into the ISR
In the ISR, the CPU clears the GPU_GP_IN_REQ_req bit
Clearing of GPU_IN_REQ_req de-asserts gpio_rx_req.
Upon gpio_rx_req de-assertion, the GPU Firmware processor enters the ackn state
The GPU Firmware processor deasserts the gpio_rx_ack signal.
De-assertion of gpio_rx_ack clears the GPU_GP_IN_ACK_ack bit enabling initiation of a new transfer
Shows that CPU must poll the GPU_GP_IN_ACK_ack bit for ‘0’ at the beginning of the send operation, to ensure that the GPU has released the gpio_rx_ack signal. It must not set GPU_GP_IN_REQ.req here or an extra gpu_gpio_ackint will be generated.
Shows that the CPU has polled GPU_GP_IN_ACK_ack low and may begin a new transfer.

GPU Power Management

The GPU includes a power management control interface to allow the GPU integrated firmware processor to interact with the SoC power management solution in order to throttle GPU power during idle time. A general description of the power management procedure is a follows:

The GPU Firmware processor initiates a power control operation by outputting the type, domain, and gpu mask values to indicate the type of request and activating the pwrctrl_req output. This generates a gpu_pwrctrl_req interrupt to the SoC Power Management (PM) processor.
The PM processor reads the requested command from the associated GPU_PWR_REQ register.
The PM processor will execute the requested Power Control request (through standard LPSC control processes).
Upon completion of the command the PM processor will set the complete (if successful) or abort (if unsuccessful) bits of the associated GPU_PWR_ACK register.
Upon receiving an active complete or abort input, the GPU Firmware processor will de-assert the pwrctrl_req output cleating the interrupt and clearing the GPU_PWR_ACK complete and abort bits.