There are four clock domain in the CSI_RX_IF.
- The CSI_RX_MAIN_CLK clock runs the CSI2 core, PSIL DMA, and retransmitts to CSI_TX_IF. The minimum clock rate for the CSI_RX_MAIN_CLK is 312.5MHz when DPHY is at max data rate (slower clock permissible when DPHY is at lower data rates). When CSI_RX_MAIN_CLK is operating lower than 312.5MHz, then the clock is essentially limiting the clock rate of the DPHY_RX. Said another way, CSI_RX_MAIN_CLK must be at least the CSI_RX_BYTE_CLK rate, else FIFOs will overflow.
The maximum clock rate is 500MHz 16ffc, 650 Max
f(CSI_RX_BYTE_CLK) × nb_lanes / 4; where f(CSI_RX_BYTE_CLK) is the minimum frequency of CSI_RX_BYTE_CLK. - The CSI_RX_VBUS_CLK is the interface configuration clock that runs at half the speed of the CSI_RX_MAIN_CLK.
- The CSI_RX_VP_CLK is the video port interface clock. It must run at the same speed or higher than CSI_RX_MAIN_CLK. It can be async to CSI_RX_MAIN_CLK clock. It also must be sync to VPAC video clock. Up to 720MHz max rate
- The CSI_RX_BYTE_CLK is the clock supplied by the DPHY_RX PLL and is divided down to byte clock. The DPHY_RX is designed for max of 10gbps. This translates to a max byte clock of 312.5MHz. The clock is inactive when DPHY_RX is not in HS operation.
Table 12-392 shows the CSI_RX_IF and DPHY_RX inter-clock dependencies.
Table 12-392 CSI_RX_IF Inter-clock Dependencies | CSI_RX_MAIN_CLK | CSI_RX_VBUS_CLK | CSI_RX_VP_CLK | CSI_RX_BYTE_CLK |
|---|
| Min freq | CSI_RX_BYTE_CLK freq | CSI_RX_MAIN_CLK / 2 freq | CSI_RX_BYTE_CLK freq | N/A |
| Max freq | 500MHz | CSI_RX_MAIN_CLK / 2 freq | 720MHz | 312.5MHz |