SPRUJ28E November 2021 – September 2024 AM68 , AM68A , TDA4AL-Q1 , TDA4VE-Q1 , TDA4VL-Q1
The waveforms in this chapter show the EPWMs behavior for a static compare register value. In a running system, the active compare registers (EPWM_CMPA and EPWM_CMPB) are typically updated from their respective shadow registers once every period. The user specifies when the update will take place — either when the time-base counter reaches zero or when the time-base counter reaches period. There are some cases when the action based on the new value can be delayed by one period or the action based on the old value can take effect for an extra period. Some PWM configurations avoid this situation. These include, but are not limited to, the following:
Use up-down-count mode to generate a symmetric PWM:
This means there will always be a pulse of at least one TBCLK cycle in a PWM period which, when very short, tend to be ignored by the system.
Use up-down-count mode to generate an asymmetric PWM:
When using up-count mode to generate an asymmetric PWM:
Figure 6-163 shows how a symmetric PWM waveform can be generated using the up-down-count mode of the TBCNT. In this mode 0-100% DC modulation is achieved by using equal compare matches on the up count and down count portions of the waveform. In the example shown, CMPA is used to make the comparison. When the counter is incrementing the CMPA match will pull the PWM output high. Likewise, when the counter is decrementing the compare match will pull the PWM signal low. When CMPA = 0, the PWM signal is low for the entire period giving the 0% duty waveform. When EPWM_CMPA = EPWM_TBPRD, the PWM signal is high achieving 100% duty.
When using this configuration in practice, if CMPA/CMPB is loaded on zero, then use CMPA/CMPB values greater than or equal to 1. If CMPA/CMPB is loaded on period, then use CMPA/CMPB values less than or equal to TBPRD - 1. This means there will always be a pulse of at least one TBCLK cycle in a PWM period which, when very short, tend to be ignored by the system.
The PWM waveforms in Figure 12-197 through Figure 12-202 show some common action-qualifier configurations. Some conventions used in the figures are as follows:
Table 12-262 and Table 12-263 contains initialization and runtime register configurations for the waveforms in Figure 12-197.
Register | Bitfield | Value | Comments |
---|---|---|---|
EPWM_TBPRD | TBPRD | 600 (258h) | Period = 601 TBCLK counts |
EPWM_TBPHS | TBPHS | 0 | Clear Phase Register to 0 |
EPWM_TBCNT | TBCNT | 0 | Clear TB counter |
EPWM_TBCTL | CTRMODE | TB_UP | |
PHSEN | TB_DISABLE | Phase loading disabled | |
PRDLD | TB_SHADOW | ||
SYNCOSEL | TB_SYNC_DISABLE | ||
HSPCLKDIV | TB_DIV1 | TBCLK = FICLK | |
CLKDIV | TB_DIV1 | ||
EPWM_CMPA | CMPA | 350 (15Eh) | Compare A = 350 TBCLK counts |
EPWM_CMPB | CMPB | 200 (C8h) | Compare B = 200 TBCLK counts |
EPWM_CMPCTL | SHDWAMODE | CC_SHADOW | |
SHDWBMODE | CC_SHADOW | ||
LOADAMODE | CC_CTR_ZERO | Load on TBCNT = 0 | |
LOADBMODE | CC_CTR_ZERO | Load on TBCNT = 0 | |
EPWM_AQCTLA | ZRO | AQ_SET | |
CAU | AQ_CLEAR | ||
EPWM_AQCTLB | ZRO | AQ_SET | |
CBU | AQ_CLEAR |
Register | Bitfield | Value | Comments |
---|---|---|---|
EPWM_CMPA | CMPA | Duty1A | Adjust duty for output EPWM1A |
EPWM_CMPB | CMPB | Duty1B | Adjust duty for output EPWM1B |
Table 12-264 and Table 12-265 contains initialization and runtime register configurations for the waveforms in Figure 12-198.
Register | Bitfield | Value | Comments |
---|---|---|---|
EPWM_TBPRD | TBPRD | 600 (258h) | Period = 601 TBCLK counts |
EPWM_TBPHS | TBPHS | 0 | Clear Phase Register to 0 |
EPWM_TBCNT | TBCNT | 0 | Clear TB counter |
EPWM_TBCTL | CTRMODE | TB_UP | |
PHSEN | TB_DISABLE | Phase loading disabled | |
PRDLD | TB_SHADOW | ||
SYNCOSEL | TB_SYNC_DISABLE | ||
HSPCLKDIV | TB_DIV1 | TBCLK = FICLK | |
CLKDIV | TB_DIV1 | ||
EPWM_CMPA | CMPA | 350 (15Eh) | Compare A = 350 TBCLK counts |
EPWM_CMPB | CMPB | 200 (C8h) | Compare B = 200 TBCLK counts |
EPWM_CMPCTL | SHDWAMODE | CC_SHADOW | |
SHDWBMODE | CC_SHADOW | ||
LOADAMODE | CC_CTR_ZERO | Load on TBCNT = 0 | |
LOADBMODE | CC_CTR_ZERO | Load on TBCNT = 0 | |
EPWM_AQCTLA | PRD | AQ_CLEAR | |
CAU | AQ_SET | ||
EPWM_AQCTLB | PRD | AQ_CLEAR | |
CBU | AQ_SET |
Register | Bit | Value | Comments |
---|---|---|---|
EPWM_CMPA | CMPA | Duty1A | Adjust duty for output EPWM1A |
EPWM_CMPB | CMPB | Duty1B | Adjust duty for output EPWM1B |
Table 12-266 and Table 12-267 contains initialization and runtime register configurations for the waveforms Figure 12-199. Use the code in Constant Definitions Used in the EPWM Code Examples to define the headers.
Register | Bitfield | Value | Comments |
---|---|---|---|
EPWM_TBPRD | TBPRD | 600 (258h) | Period = 601 TBCLK counts |
EPWM_TBPHS | TBPHS | 0 | Clear Phase Register to 0 |
EPWM_TBCNT | TBCNT | 0 | Clear TB counter |
EPWM_TBCTL | CTRMODE | TB_UP | |
PHSEN | TB_DISABLE | Phase loading disabled | |
PRDLD | TB_SHADOW | ||
SYNCOSEL | TB_SYNC_DISABLE | ||
HSPCLKDIV | TB_DIV1 | TBCLK = FICLK | |
CLKDIV | TB_DIV1 | ||
EPWM_CMPA | CMPA | 200 (C8h) | Compare A = 200 TBCLK counts |
EPWM_CMPB | CMPB | 400 (190h) | Compare B = 400 TBCLK counts |
EPWM_CMPCTL | SHDWAMODE | CC_SHADOW | |
SHDWBMODE | CC_SHADOW | ||
LOADAMODE | CC_CTR_ZERO | Load on TBCNT = 0 | |
LOADBMODE | CC_CTR_ZERO | Load on TBCNT = 0 | |
EPWM_AQCTLA | CAU | AQ_SET | |
CBU | AQ_CLEAR | ||
EPWM_AQCTLB | ZRO | AQ_TOGGLE |
Register | Bitfield | Value | Comments |
---|---|---|---|
EPWM_CMPA | CMPA | EdgePosA | Adjust duty for output EPWM1A |
EPWM_CMPB | CMPB | EdgePosB |
Table 12-268 and Table 12-269 contains initialization and runtime register configurations for the waveforms in Figure 12-200. Use the code in Constant Definitions Used in the EPWM Code Examples to define the headers.
Register | Bitfield | Value | Comments |
---|---|---|---|
EPWM_TBPRD | TBPRD | 600 (258h) | Period = 601 TBCLK counts |
EPWM_TBPHS | TBPHS | 0 | Clear Phase Register to 0 |
EPWM_TBCNT | TBCNT | 0 | Clear TB counter |
EPWM_TBCTL | CTRMODE | TB_UPDOWN | |
PHSEN | TB_DISABLE | Phase loading disabled | |
PRDLD | TB_SHADOW | ||
SYNCOSEL | TB_SYNC_DISABLE | ||
HSPCLKDIV | TB_DIV1 | TBCLK = FICLK | |
CLKDIV | TB_DIV1 | ||
EPWM_CMPA | CMPA | 400 (190h) | Compare A = 400 TBCLK counts |
EPWM_CMPB | CMPB | 500 (1F4h) | Compare B = 500 TBCLK counts |
EPWM_CMPCTL | SHDWAMODE | CC_SHADOW | |
SHDWBMODE | CC_SHADOW | ||
LOADAMODE | CC_CTR_ZERO | Load on TBCNT = 0 | |
LOADBMODE | CC_CTR_ZERO | Load on TBCNT = 0 | |
EPWM_AQCTLA | CAU | AQ_SET | |
CAD | AQ_CLEAR | ||
EPWM_AQCTLB | CBU | AQ_SET | |
CBD | AQ_CLEAR |
Register | Bitfield | Value | Comments |
---|---|---|---|
EPWM_CMPA | CMPA | Duty1A | Adjust duty for output EPWM1A |
EPWM_CMPB | CMPB | Duty1B | Adjust duty for output EPWM1B |
Table 12-270 and Table 12-271 contains initialization and runtime register configurations for the waveforms in Figure 12-201. Use the code in Constant Definitions Used in the EPWM Code Examples to define the headers.
Register | Bitfield | Value | Comments |
---|---|---|---|
EPWM_TBPRD | TBPRD | 600 (258h) | Period = 601 TBCLK counts |
EPWM_TBPHS | TBPHS | 0 | Clear Phase Register to 0 |
EPWM_TBCNT | TBCNT | 0 | Clear TB counter |
EPWM_TBCTL | CTRMODE | TB_UPDOWN | |
PHSEN | TB_DISABLE | Phase loading disabled | |
PRDLD | TB_SHADOW | ||
SYNCOSEL | TB_SYNC_DISABLE | ||
HSPCLKDIV | TB_DIV1 | TBCLK = FICLK | |
CLKDIV | TB_DIV1 | ||
EPWM_CMPA | CMPA | 350 (15Eh) | Compare A = 350 TBCLK counts |
EPWM_CMPB | CMPB | 400 (190h) | Compare B = 400 TBCLK counts |
EPWM_CMPCTL | SHDWAMODE | CC_SHADOW | |
SHDWBMODE | CC_SHADOW | ||
LOADAMODE | CC_CTR_ZERO | Load on TBCNT = 0 | |
LOADBMODE | CC_CTR_ZERO | Load on TBCNT = 0 | |
EPWM_AQCTLA | CAU | AQ_SET | |
CAD | AQ_CLEAR | ||
EPWM_AQCTLB | CBU | AQ_CLEAR | |
CBD | AQ_SET |
Register | Bitfield | Value | Comments |
---|---|---|---|
EPWM_CMPA | CMPA | Duty1A | Adjust duty for output EPWM1A |
EPWM_CMPB | CMPB | Duty1B | Adjust duty for output EPWM1B |
Table 12-272 and Table 12-273 contains initialization and runtime register configurations for the waveforms in Figure 12-202. Use the code in Constant Definitions Used in the EPWM Code Examples to define the headers.
Register | Bitfield | Value | Comments |
---|---|---|---|
EPWM_TBPRD | TBPRD | 600 (258h) | Period = 601 TBCLK counts |
EPWM_TBPHS | TBPHS | 0 | Clear Phase Register to 0 |
EPWM_TBCNT | TBCNT | 0 | Clear TB counter |
EPWM_TBCTL | CTRMODE | TB_UPDOWN | |
PHSEN | TB_DISABLE | Phase loading disabled | |
PRDLD | TB_SHADOW | ||
SYNCOSEL | TB_SYNC_DISABLE | ||
HSPCLKDIV | TB_DIV1 | TBCLK = FICLK | |
CLKDIV | TB_DIV1 | ||
EPWM_CMPA | CMPA | 250 (FAh) | Compare A = 250 TBCLK counts |
EPWM_CMPB | CMPB | 450 (1C2h) | Compare B = 450 TBCLK counts |
EPWM_CMPCTL | SHDWAMODE | CC_SHADOW | |
SHDWBMODE | CC_SHADOW | ||
LOADAMODE | CC_CTR_ZERO | Load on TBCNT = 0 | |
LOADBMODE | CC_CTR_ZERO | Load on TBCNT = 0 | |
EPWM_AQCTLA | CAU | AQ_SET | |
CBD | AQ_CLEAR | ||
EPWM_AQCTLB | ZRO | AQ_CLEAR | |
PRD | AQ_SET |
Register | Bitfield | Value | Comments |
---|---|---|---|
EPWM_CMPA | CMPA | EdgePosA | Adjust duty for output EPWM1A |
EPWM_CMPB | CMPB | EdgePosB | Adjust duty for output EPWM1B |