SPRUJ28E November 2021 – September 2024 AM68 , AM68A , TDA4AL-Q1 , TDA4VE-Q1 , TDA4VL-Q1
The MSMC2DDR bridge checks the VBUSM.C opcode received for unsupported opcodes and flags error for debug purposes. Only opcode values for read and write operations are supported.
If an unsupported VBUSM.C opcode is received for an access, the bridge sets the DDRSS_V2A_INT_RAW_REG[0] OERR bit to 0x1 and triggers the DDR0_DDRSS_V2A_OTHER_ERR_LVL_0 interrupt. The opcode and the Route ID for the command caused error are logged in the DDRSS_V2A_OERR_LOG_REG[17-12] OERR_OP_CODE and DDRSS_V2A_OERR_LOG_REG[11-0] OERR_ROUTE_ID fields.
Since the bridge does not know how to process the command with an unsupported opcode, it discards the command and does not respond with any status on the write status or the read status buses.