The Navigator subsystem (NAVSS) can be used for
efficient transfer of data support between software, firmware and hardware in all
combinations. It consists of the following main modules:
- Unified DMA Controller with
the following main modes and features:
- K3 DMA Architecture
compliant Tx/Rx port implementation
- K3 DMA Architecture
compliant Packet-Oriented DMA Functionality (UDMA-P)
- K3 DMA Architecture
compliant Third Party Channel Controller
- K3 DMA Architecture
compliant Unified Transfer Controller
- K3 DMA Architecture
compliant Unified DMA channels which all share the execution
hardware using time division multiplexing
- Ring Accelerator provides
hardware acceleration to enable straightforward passing of work between a
producer and a consumer and has the following main features:
- Supports 1024
independent memory-mapped ring structures
- Supports various
modes for each ring based on usage and compatibility
- Provides 2-words deep
shared incoming Transfer Response FIFO
- Provides bit-wide
source VBUSM read/write slave interface for accesses from DMA
controller entities
- Proxy module with the
following main features:
- Provides proxy
buffers to store large data bursts that a host can only access in
smaller amounts
- Keeps the large data
coherent until the complete data has been accessed
- Allows interleaved
access between multiple hosts using multiple proxies
- Supports a
pre-configured number of target resources to proxy with
pre-configured number of channels, size of each channel, and address
offset per each target
- Secure proxy module is a
modified version of the proxy module and in addition has the following main
features:
- Supports a number of
threads, where each has their own independent proxy function
- Supports a
programmable fixed queue for each proxy thread
- Supports multiple
producers all writing to the same queue
- Supports programmable
thresholds for when to generate events
- Supports a max
message count for outbound proxy threads limiting the number of
messages a thread can produce
- Interrupt Aggregator modules
provide a centralized machine which handles the termination of system events
to that they can be coherently processed by the host(s) in the system. Main
features are as follows:
- 64-bit VBUSP slave
using 64-bit registers
- Provide a set of TI
Interrupt Architecture compliant interrupt status and mask registers
which are used to pass specific event status to one or more host
blocks.
- Provide a set of
Global Event Input (GEVI) counters which can count events delivered
via an ingress Event Transport Lane (ETL)
- Provides a set of
Local Event Input (LEVI) to Global event registers which can be used
to convert pulsed discrete interrupt inputs or clock synchronous
rising edge events into Global events on an egress ETL
- Provides a set of
GEVI 'Multicast' registers which can take a Global event from an
ingress ETL and generate two egress Global events on two egress ETL
interfaces
- Peripheral Virtualization
Unit (PVU) module which provides TLBs (Translation Look-aside Buffers) for
static virtual address translation on a CBA VBUSM bus with the following
main features:
- Implements a
channelized TLB for virtual address translation
- Supports a
pre-configured number of entries per TLB channel
- Supports TLB chaining
to extend the search but at a latency penalty
- Supports a 48-bit
address size
- Supports page sizes
of 4KB, 16KB, 64KB, 2MB, 32MB, 512MB, 1GB, and 16GB
- Support TLBs in
software mode, where they are maintained by software only
- Produces a fault
interrupt when the TLB misses or upon a permission error
- Mailbox module to facilitate
the communication between the various on-chip processors of the device by
providing a queued mailbox-interrupt mechanism with the following main
features:
- 12 clusters
- 32-bit message
width
- Message reception and
queue-not-full notification using interrupts
- Non-intrusive
emulation
- Spinlock module (256 hardware
semaphores) for synchronizing the processes running on multiple processors
in the device.
- Timer Manager modules to
support timing operations for the processes running on multiple processors,
with the following main features:
- 1024 × 32-bit
RAM-based independent timers (2048 in total)
- Event interface to an
interrupt aggregation module in the NAVSS subsystem with events
triggering when a timer expires or when an expired timer is reset or
deactivated
- Host access to
determine which timer(s) expired
- 32 registers with
individual timeout status (one bit per timer)
- Groups of 16 timers
separated into pages of 4-K address space
- Timer bits within
each page to read expiration status for each timer when software
only has access to that page
- 10 μs time to cycle
through all of the timers
- Host access to reset
individual timers
- Periodic hardware
timers – a timer may be set to automatically reprogram itself upon
expiration without software intervention.
- Time Sync modules to
facilitate host control of time sync operations, each with the following
main features:
- Supports a selection
of multiple external clock sources
- Software control of
time sync events via interrupt or polling
- Supports 8 hardware
timestamp push inputs
- Supports timestamp
counter compare output
- Supports timestamp
counter bit output
- Supports 6 timestamp
generator function outputs
- 32-bit and 64-bit
timestamp modes
- Memory Cyclic Redundancy
Check module used to perform CRC to verify the integrity of a memory system
with the following main features:
- Four channels to
perform background signature verification on any memory
subsystem
- Data compression on
8-, 16-, 32-, and 64-bit data size
- Dedicated CRC value
register per channel which contains the pre-determined CRC
value
- Timed base event
trigger from timer to initiate DMA data transfer
- Programmable 20-bit
pattern counter per channel to count the number of data patterns for
compression
- Three modes of
operation: Auto, Semi-CPU, and Full-CPU
- Timeout interrupt
generation if CRC is not performed within the time limit
- Per channel DMA
request generation to initiate CRC value transfer