SPRUJ28E November 2021 – September 2024 AM68 , AM68A , TDA4AL-Q1 , TDA4VE-Q1 , TDA4VL-Q1
The write DMA buffer is used by the WB pipeline.
Two modes for filling the DMA buffer are supported by the WB channel, selectable through the DSS0_WB_ATTRIBUTES[19] WRITEBACKMODE bit:
In capture mode: Transfer is synchronous (that is, tightly coupled) to one of the display outputs. In this mode, the write back buffer starts receiving data after DSS0_WB_ATTRIBUTES[0] ENABLE register bit has been set and the associated output vertical sync has triggered the start of the transfer (VFP). In addition, the WB ENABLE bit shall be set prior to the enable of the captured channel output in order to capture the first frame.
In memory-to-memory mode: The data transfer is not synchronous to any of the display outputs. In this mode, the write back buffer starts receiving data after the DSS0_WB_ATTRIBUTES[0] ENABLE has been set. The WB ENABLE bit also is triggering the update of the shadow register in the WB pipeline.
Programmable high and low thresholds are used by the DMA engine to start and stop sending data to the system interconnect.
At the end of the frame, to completely drain the DMA buffer, some smaller bursts (even single requests) may have to be issued. To limit the number of interconnect requests from the DISPC (that is, to limit the throughput of the write-back channel to the memory), a number of IDLE cycles between requests can be inserted. IDLE cycles can be inserted only when WB is used in memory-to-memory mode. It is ignored when WB is in capture mode.
The number of IDLE cycles between requests can be activated and determined by: