SPRUJ28E November 2021 – September 2024 AM68 , AM68A , TDA4AL-Q1 , TDA4VE-Q1 , TDA4VL-Q1
The DCC can be programmed to count down one time using single-shot mode. In this mode, the DCC stops operation when both COUNT0 and VALID0 reach 0.
At the end of one sequence in single-shot mode the DCC_GCTRL[3-0] DCCENA bitfield is set to disabled, which stops further counting. Single-shot mode is enabled from the DCC_GCTRL[11-8] SINGLESHOT bitfield.
At the end of one sequence in single-shot mode, if there is no error which stops counting, then the done status bit is set in the DCC_STAT[1] DONEFLG bitfield and a done interrupt DCCx_INTR_DONE_LEVEL is generated. Software must clear the done bit before restarting the counting.