The DDR subsystem in this device comprises DDR
controller, DDR PHY and wrapper logic to integrate these blocks in the device. The
DDR subsystem is referred to as DDRSS and
is used to provide an interface to external SDRAM devices which can be utilized for
storing program or data. DDRSS is accessed
via MSMC, and not directly through the system interconnect.
The DDRSS
supports:
- Memory Types:
- Memory Bus Features:
- 32-bit width with
in-line ECC
- Up to 2 ranks (in one
package)
- SDRAM address range
up to 8 GB
- System Bus Interface:
- 512-bit data
width
- Little endian
only
- Address aliasing
prevention to block accesses to unpopulated SDRAM region
- Clock asynchronous to
DDR clock
- Configuration Bus Interface:
- 32-bit data
width
- Linear incrementing
addressing mode
- 32-bit aligned
accesses only
- Little endian
only
- Clock asynchronous to
DDR clock
- Key Features:
- Full coherency across
all commands
- Bank
interleaving
- Priority based
scheduling
- Scheduling based on
bank openness
- Class of Service
(CoS) - Three latency classes supported
- Read/write scheduling
to avoid turn-around time
- Prioritized refresh
scheduling
- Dynamic change of
refresh rate via software for extended temperatures
- Statistical counters
for performance management
- SDRAM ECC Features:
- In-line ECC
- Read-modify-write ECC
for sub-word writes
- ECC address error
logging
- Statistical counters
for counting ECC errors
- Injecting ECC errors
during normal operation for validation
- Low Power Features:
- Self-refresh entry
and exit via software or hardware clock stop request
- System bus clock stop
via hardware clock stop request when controller is idle
- Automatic idle power
saving mode when no or low activity is detected
- DDR and system bus
clock frequency change using self-refresh via software or hardware
clock stop request
- Turning off SoC power
after DDR is put into self-refresh (DDR reset and CKE I/O
retention)
- Tri-stating of all
DDR I/O cells via software while driving CKE and RSTN pins during
self-refresh
- LPDDR4 Frequency Set
Point (FSP)
- I/O retention managed
by an external device through dedicated pin
- Functional Reliability
Features:
- ECC on data pipe
- Parity on address and
command pipes
- Data EDC on the
master port interface
- Command parity on the
master port interface
- Data EDC on the
configuration port interface
- Command parity on the
configuration port interface
- MSMC2DDR bridge AXI
bus timeout
- DDR PHY Features:
- Automatic and
software controllable initialization and calibration (ZQ) for the
DDR PHY and I/O cells
- Automatic and
software controllable delay line calibrations with Voltage and
Temperature (VT) compensation
- Automatic and
software controllable write levelling with VT compensation
- Automatic read DQS
gate training per rank with VT compensation
- Automatic and
software controllable DQ/DQS eye training per rank
- Automatic and
software controllable read and write data bit deskew
- Automatic and
software controllable Command/Address (CA) levelling with VT
compensation for LPDDR4
- Automatic and
software controllable CA bit deskew for LPDDR4
- Refreshes to SDRAM
during leveling and training
- No seeding
requirement based on board topology for any of the leveling and
training algorithms
- Dynamic/automatic I/O
Receiver disable when read transfer is not on going
- Capability of
disabling data macros and I/O cells when not in use