SPRUJ28E November 2021 – September 2024 AM68 , AM68A , TDA4AL-Q1 , TDA4VE-Q1 , TDA4VL-Q1
When a transition is detected on the module input pin (PIEVENTCAPT), the timer value in the TIMER_TCRR can be captured and saved in the TIMER_TCAR1 or TIMER_TCAR2 register function of the mode selected in the TIMER_TCLR[13] CAPT_MODE bit. The edge detection circuitry monitors transitions on the input pin (PIEVENTCAPT).
The rising edge, falling edge, or both, can be selected in the TIMER_TCLR[9-8] TCM bit field to trigger the timer counter capture. The module sets the TIMER_IRQSTATUS[2] TCAR_IT_FLAG bit when an active edge is detected, and at the same time, the counter value TIMER_TCRR is stored in timer capture register TIMER_TCAR1 or TIMER_TCAR2, as follows:
The edge detection logic is reset (a new capture is enabled) when the active capture interrupt is served. The TIMER_IRQSTATUS[2] TCAR_IT_FLAG bit is cleared by writing 1 to it or when the edge detection mode bits (the TIMER_TCLR[9-8] TCM bit field) are changed from no-capture mode detection to any other mode. The timer functional clock (input to prescaler) is used to sample the input pin (PIEVENTCAPT). A negative or positive pulse input can be detected when the pulse time is greater than the functional clock period. An interrupt is issued on edge detection if the capture interrupt-enable bit is set in the TIMER_IRQSTATUS_SET[2] TCAR_EN_FLAG bit. See the examples in Figure 12-485 and Figure 12-486.
In Figure 12-485, the value of the TIMER_TCLR[9-8] TCM bit field is 1h, and the TIMER_TCLR[13] CAPT_MODE bit is 0. Only the rising edge of PIEVENTCAPT triggers a capture in the TIMER_TCAR1 and TIMER_TCAR2 registers, and only the TIMER_TCAR1 register updates.
In Figure 12-486, the value of the TIMER_TCLR[9-8] TCM bit field is 1h, and the TIMER_TCLR[13] CAPT_MODE bit is 1. Only the rising edge of PIEVENTCAPT triggers a capture in the TIMER_TCAR1 register on the first enabled event, and the TIMER_TCAR2 register updates on the second enabled event.