SPRUJ28E November 2021 – September 2024 AM68 , AM68A , TDA4AL-Q1 , TDA4VE-Q1 , TDA4VL-Q1
Figure 12-169 shows how the ECAP module can be used to collect Delta timing data from pulse train waveforms. Here Continuous Capture mode (TSCTR counts-up without resetting, and Mod4 counter wraps around) is used. In Delta-time mode, TSCTR is Reset back to Zero on every valid event. Here Capture events are qualified as Rising edge only. On an event, TSCTR contents (time-stamp) is captured first, and then TSCTR is reset to Zero. The Mod4 counter then increments to the next state. If TSCTR reaches FFFF FFFFh (maximum value), before the next event, it wraps around to 0000 0000h and continues, a CNTOVF_FLG (counter overflow) Flag is set, and an Interrupt (if enabled) occurs. The advantage of Delta-time Mode is that the CAPn contents directly give timing data without the need for CPU calculations: Period1 = T1, Period2 = T2,…etc. As shown in Figure 12-169, the CEVT1 event is a good trigger point to read the timing data, T1, T2, T3, T4 are all valid here.
Register | Bit | Value |
---|---|---|
ECCTL1 | CAP1POL | EC_RISING |
ECCTL1 | CAP2POL | EC_RISING |
ECCTL1 | CAP3POL | EC_RISING |
ECCTL1 | CAP4POL | EC_RISING |
ECCTL1 | CTRRST1 | EC_DELTA_MODE |
ECCTL1 | CTRRST2 | EC_DELTA_MODE |
ECCTL1 | CTRRST3 | EC_DELTA_MODE |
ECCTL1 | CTRRST4 | EC_DELTA_MODE |
ECCTL1 | CAPLDEN | EC_ENABLE |
ECCTL1 | PRESCALE | EC_DIV1 |
ECCTL2 | CAP_APWM | EC_CAP_MODE |
ECCTL2 | CONT_ONESHT | EC_CONTINUOUS |
ECCTL2 | SYNCO_SEL | EC_SYNCO_DIS |
ECCTL2 | SYNCI_EN | EC_DISABLE |
ECCTL2 | TSCTRSTOP | EC_RUN |