SPRUJ28E November 2021 – September 2024 AM68 , AM68A , TDA4AL-Q1 , TDA4VE-Q1 , TDA4VL-Q1
The GIC uses the AXI4 master interface to allow the ITS and redistributors to access main memory. It is expected that the main memory (attached to a CBASS VBUSM port) holds the following:
The AXI2VBUSM bridge converts the standard 64-bit AXI4 master interface into a pair of 64-bit VBUSM write-only and read-only master interfaces. AXI4 has a separate command channel for read and write, and the AXI2VBUSM bridge keeps them separate, so that the system may prioritize or arbitrate the traffic between them as appropriate.
The GIC uses the AXI4 slave interface to provide access to the programming interfaces of all its parts (distributor, redistributors, ITS). The VBUSM2AXI bridge converts the standard 32-bit VBUSM master interface into an 32-bit AXI4 slave interface.
The AXI2VBUSM and VBUSM2AXI bridges do not implement any MMRs.