SPRUJ28E November 2021 – September 2024 AM68 , AM68A , TDA4AL-Q1 , TDA4VE-Q1 , TDA4VL-Q1
LPDDR4 supports termination for the DQ and DQS input signals, but this termination does not utilize an ODT input pin. Instead, the ODT is controlled by the command. The functionality is enabled through bits [2-0] of mode register MR11, where a value of 0h disables the ODT functionality. The DQ ODT settings can be programmed through the following fields:
These field values are written to the associated mode registers when the DDR controller issues a MRW to the memory.
When DQ ODT is enabled, RTT is asserted with a write or masked write command.