A state machine inside the DDR controller tracks oscillator-related commands and wait times. The basic flow is as follows:
- If the oscillator function is enabled by setting
the DDRSS_CTL_26[16] DQS_OSC_ENABLE bit to 1h, the process begins when a
request is received to run the oscillator function. This request can be
issued automatically during the initialization process, during a frequency
change process, as a software request by setting the DDRSS_CTL_30[0]
DQS_OSC_REQUEST bit to 1h, or through a programmable periodic timer (the
DDRSS_CTL_28[23-16] DQS_OSC_NORM_THRESHOLD, DDRSS_CTL_28[31-24]
DQS_OSC_HIGH_THRESHOLD, or DDRSS_CTL_29[7-0] DQS_OSC_TIMEOUT fields). Once
this process has started, the memory is not allowed to enter any low power
modes until complete.
- If the request is through initialization, MR23 is
written with the value of the DDRSS_CTL_190[7-0] MR23_DATA field defining
the number of cycles to run the oscillator.
- An MPC is issued to start the oscillator. If there are multiple DRAM devices on a rank, the MPC is issued to all devices on the rank at the same time, and then the state machine proceeds to the next rank and issues MPCs to that rank, and so on.
- The state machine waits the cycles defined by the
DDRSS_CTL_27[14-0] DQS_OSC_PERIOD field and the cycles specified in the
DDRSS_CTL_27[31-24] TOSCO_F0, DDRSS_CTL_28[7-0] TOSCO_F1, and
DDRSS_CTL_28[15-8] TOSCO_F2 fields to allow the operation to complete and
the results to be stored.
- The state machine issues a read to MR18.
- The state machine waits the number of cycles
specified in the DDRSS_CTL_51[27-24] TMRR field, and then stores the result
in a temporary location. If there are multiple DRAM devices on a rank, the
MRR captures the mode register content for all devices on that rank.
- The state machine issues a read to MR19.
- The state machine waits the number of cycles
specified in the DDRSS_CTL_51[27-24] TMRR field, and then stores the result
in a temporary location. If there are multiple DRAM devices on a rank, the
MRR captures the mode register content for all devices on that rank.
- The values read in MR18 and MR19 represent the LSB and MSB of the DQS oscillator count. The DDR controller combines them and compares the result. If multiple devices exist on a rank, the comparison is made between each device and the base value.
- If this is the initial read or a read related to
a DFS operation, the values are stored in the OSC_BASE_VALUE_x_CSy
fields. The DDR controller drives a 1h value on the dfi_function
signal and asserts the dfi_function_valid signal for the number of
cycles defined by the DDRSS_CTL_27[19-16] FUNC_VALID_CYCLES
field.
- If the value is FFFFh, an overflow condition
occurred during the measurement process. The DDR controller sets to
1h bit [0] in the DDRSS_CTL_294[12-0] INT_STATUS_1 field indicating
DQS oscillator measurement overflow interrupt and ignores the
value.
- If the difference between the measured value and
the base value is lower than or equal to the value programmed in the
DDRSS_CTL_29[31-16] OSC_VARIANCE_LIMIT field, the DDR controller
returns to idle state. If the request was issued through software,
the DDR controller sets to 1h bit [30] in the DDRSS_CTL_293[31-0]
INT_STATUS_0 field indicationg DQS oscillator request complete
interrupt.
- If the difference between the measured value and
the base value is greater than the value programmed in the
DDRSS_CTL_29[31-16] OSC_VARIANCE_LIMIT field, the DDR controller
sets to 1h bit [1] in the DDRSS_CTL_294[12-0] INT_STATUS_1 field
indicating DQS oscillator out of variance interrupt. The DDR
controller also drives a 2h value on the dfi_function signal and
asserts the dfi_function_valid signal for the number of cycles
defined by the DDRSS_CTL_27[19-16] FUNC_VALID_CYCLES field. The
measured value will replace the base value for any device for which
the measured value is outside the variance. This base value update
does not set to 1h bit [31] in the DDRSS_CTL_293[31-0] INT_STATUS_0
field.