SPRUJ28E November 2021 – September 2024 AM68 , AM68A , TDA4AL-Q1 , TDA4VE-Q1 , TDA4VL-Q1
LPDDR4 can terminate the CA bus, including the CS and CLK signals. The value on the ODT input pin, ODT_CA, on the DRAM and the settings in the mode registers determine if CA ODT is enabled in the memories and the RTT termination resistance. The functionality is enabled through bits [6-4] of mode register MR11, where the value of 0h disables ODT functionality. Bits [5-3] of MR22 control individual aspects of the CA ODT when ODT is not disabled. The CA ODT settings can be programmed through the following fields:
These field values are written to the associated mode registers when the DDR controller issues a MRW to the memory.