SPRUJ28E November 2021 – September 2024 AM68 , AM68A , TDA4AL-Q1 , TDA4VE-Q1 , TDA4VL-Q1
The TLB entry contains permissions for the page that must be checked before the translation can be used. These include if the page has supervisor access for read, write, or execute, and has user access for read, write, or execute. The supervisor or user is based on the transaction priv[0] signal (0 = user, 1 = supervisor). The access type is based on the transaction dtype[0] and dir signals (dtype[0] = 0 and dir = 1 is a read, dtype[0] = 0 and dir = 0 is a write, dtype[0] = 1 and dir = 1 is an execute). The transaction signals are checked against these permissions. If they are allowed then the translation continues. If the page does not allow this transaction then the check fails and flush signal set is on the bus, like for a firewall, indicating that the transaction is no longer valid and must return an error. PVU does not perform the error signaling, so a later module must support it. A fault interrupt is produced.
The pperm entry bits define four additional checks. If pperm[0] is clear then user privilege access is not allowed, and a matching transaction with the CBA bus priv signal set to 0 (indicating user access) will result in an error. If pperm[1] is set then write access is not allowed, and a matching transaction that is a write will result in an error. If pperm[2] is set then instruction execute is not allowed, and a matching transaction that has the CBA bus dtype signal set to 1 (instruction fetch) will result in an error. If pperm[3] is set then supervisor instruction execute is not allowed, and a matching transaction that has the CBA bus priv signal non-zero (above user) and the CBA bus dtype signal set 1 (instruction fetch) will result in an error. If all these checks pass then the translation is allowed.
The pprefetch entry bit determines whether the translation allows prefetch transactions. If set, then any transaction with the pfable signal set are allowed. But if pprefetch=0 then those transactions with pfable set will fault as prefetch is defined as not supported.