SPRUJ28E
November 2021 – September 2024
AM68
,
AM68A
,
TDA4AL-Q1
,
TDA4VE-Q1
,
TDA4VL-Q1
1
Read This First
About This Manual
Related Documentation From Texas Instruments
Glossary
Support Resources
Export Control Notice
Release History
Trademarks
1
Introduction
1.1
Device Overview
1.1.1
Device Overview Feature List
1.1.2
Device Block Diagram
1.1.3
Modules Allocation and Instances within Device Domains
1.2
Module Descriptions
1.2.1
Arm Cortex-A72 Subsystem
1.2.2
Arm Cortex-R5F Processor
1.2.3
C71x DSP Subsystem
1.2.4
Graphics Processing Unit
1.2.5
Video Accelerator
1.2.6
Vision Pre-processing Accelerator
1.2.7
Depth and Motion Perception Accelerator
1.2.8
Navigator Subsystem
1.2.9
Region-based Address Translation Module
1.2.10
Data Routing Unit
1.2.11
Display Subsystem
1.2.12
Camera Subsystem
1.2.13
Shared D-PHY Transmitter
1.2.14
Multicore Shared Memory Controller
1.2.15
DDR Subsystem
1.2.16
General Purpose Input/Output Interface
1.2.17
Inter-Integrated Circuit Interface
1.2.18
Improved Inter-Integrated Circuit Interface
1.2.19
Multi-channel Serial Peripheral Interface
1.2.20
Universal Asynchronous Receiver/Transmitter
1.2.21
Peripheral Component Interconnect Express Subsystem
1.2.22
Universal Serial Bus (USB) Subsystem
1.2.23
SerDes
1.2.24
General Purpose Memory Controller with Error Location Module
1.2.25
Multimedia Card/Secure Digital Interface
1.2.26
Enhanced Capture Module
1.2.27
Enhanced Pulse-Width Modulation Module
1.2.28
Enhanced Quadrature Encoder Pulse Module
1.2.29
Controller Area Network
1.2.30
Audio Tracking Logic
1.2.31
Multi-channel Audio Serial Port
1.2.32
Timers
1.2.33
Internal Diagnostics Modules
1.2.34
Analog-to-Digital Converter
1.2.35
Gigabit Ethernet Switch
1.2.36
Octal Serial Peripheral Interface and HyperBus Memory Controller as a Flash Subsystem
1.2.37
Security Management Subsystem
1.3
Device Identification
2
Memory Maps
2.1
MAIN Memory Map
2.2
MCU Memory Map
2.3
WKUP Memory Map
2.4
Processors View Memory Map
2.4.1
COMPUTE_CLUSTER0 Memory Map
2.4.2
DMPAC0 Memory Map
2.4.3
R5FSS0 Memory Map
2.4.4
R5FSS1 Memory Map
2.4.5
MCU_NAVSS0 Memory Map
2.4.6
MCU_R5FSS0 Memory Map
2.4.7
MCU_SA3_SS0 Memory Map
2.4.8
WKUP_SMS0 Memory Map
2.5
Region-based Address Translation
3
System Interconnect
3.1
System Interconnect Overview
3.2
System Interconnect Functional Description
3.2.1
Quality of Service (QoS)
3.2.2
Route ID
3.2.3
Initiator-Side Security Controls (ISC)
3.2.3.1
Special System Level Priv-ID
3.2.4
Firewalls (FW)
3.2.4.1
Peripheral Firewalls (FW)
3.2.4.2
Memory or Region-based Firewalls
3.2.4.2.1
Region Based Firewall Functional Description
3.2.4.2.2
Channelized Firewalls
3.2.4.2.2.1
Channelized Firewall Functional Description
3.2.5
Null Error Reporting
3.2.6
Initiator-Target Connections
4
Initialization
4.1
Initialization Overview
4.1.1
ROM Code Overview
4.1.2
Bootloader Modes
4.1.3
Terminology
4.2
Boot Process
4.2.1
MCU ROM Code Architecture
4.2.1.1
Main Module
4.2.1.2
X509 Module
4.2.1.3
Buffer Manager Module
4.2.1.4
Log and Trace Module
4.2.1.5
System Module
4.2.1.6
Protocol Module
4.2.1.7
Driver Module
4.2.2
SMS ROM Description
4.2.3
Boot Process Flow
4.2.4
MCU Only vs Normal Boot
4.3
Boot Mode Pins
4.3.1
MCU_BOOTMODE Pin Mapping
4.3.2
BOOTMODE Pin Mapping
4.3.2.1
Primary Boot Mode Selection
4.3.2.2
Backup Boot Mode Selection When MCU Only = 0
4.3.2.3
Primary Boot Mode Configuration
4.3.2.4
Backup Boot Mode Configuration
4.3.3
No-boot/Dev-boot Configuration
4.3.4
Hyperflash Boot Device Configuration
4.3.5
OSPI Boot Device Configuration
4.3.6
QSPI Boot Device Configuration
4.3.7
SPI Boot Device Configuration
4.3.8
xSPI Boot Device Configuration
4.3.9
I2C Boot Device Configuration
4.3.10
MMC/SD Card Boot Device Configuration
4.3.11
eMMC Boot Device Configuration
4.3.11.1
eMMC Flash
4.3.12
Ethernet Boot Device Configuration
4.3.13
USB Boot Device Configuration
4.3.14
PCIe Boot Device Configuration
4.3.15
UART Boot Device Configuration
4.3.16
Serial NAND Boot Device Configuration
4.3.17
PLL Configuration
4.3.17.1
MCU_PLL0, MCU_PLL2, Main PLL0, and Main PLL3
4.3.17.2
MCU_PLL1
4.3.17.3
Main PLL1
4.3.17.4
Main PLL2
4.3.17.5
HSDIV Values
4.3.17.6
128
4.4
Boot Parameter Tables
4.4.1
Common Header
4.4.2
PLL Setup
4.4.3
PCIe Boot Parameter Table
4.4.4
I2C Boot Parameter Table
4.4.5
OSPI/QSPI/SPI Boot Parameter Table
4.4.6
Ethernet Boot Parameter Table
4.4.7
USB Boot Parameter Table
4.4.8
MMCSD Boot Parameter Table
4.4.9
UART Boot Parameter Table
4.4.10
Hyperflash Boot Parameter Table
4.4.11
Serial NAND Boot Parameter Table
4.5
Boot Image Format
4.5.1
Overall Structure
4.5.2
X.509 Certificate
4.5.3
Organizational Identifier (OID)
4.5.4
X.509 Extensions Specific to Boot
4.5.4.1
Boot Info (OID 1.3.6.1.4.1.294.1.1)
4.5.4.2
Image Integrity (OID 1.3.6.1.4.1.294.1.2)
4.5.5
Extended Boot Info Extension
4.5.5.1
Impact on HS Device
4.5.5.2
Extended Boot Info Details
4.5.5.3
Certificate / Component Types
4.5.5.4
Extended Boot Encryption Info
4.5.5.5
Component Ordering
4.5.5.6
Memory Load Sections Overlap with Executable Components
4.5.5.7
Device Type and Extended Boot Extension
4.5.6
Generating X.509 Certificates
4.5.6.1
Key Generation
4.5.6.1.1
Degenerate RSA Keys
4.5.6.2
Configuration Script
4.5.7
Image Data
4.6
Boot Modes
4.6.1
I2C Bootloader Operation
4.6.1.1
I2C Initialization Process
4.6.1.1.1
Block Size
4.6.1.1.2
165
4.6.1.2
I2C Loading Process
4.6.1.2.1
Loading a Boot Image From EEPROM
4.6.2
SPI Bootloader Operation
4.6.2.1
SPI Initialization Process
4.6.2.2
SPI Loading Process
4.6.3
QSPI Bootloader Operation
4.6.3.1
QSPI Initialization Process
4.6.3.2
QSPI Loading Process
4.6.4
OSPI Bootloader Operation
4.6.4.1
OSPI Initialization Process
4.6.4.2
OSPI Loading Process
4.6.5
PCIe Bootloader Operation
4.6.5.1
PCIe Initialization Process
4.6.5.2
PCIe Loading Process
4.6.6
Ethernet Bootloader Operation
4.6.6.1
Ethernet Initialization Process
4.6.6.2
Ethernet Loading Process
4.6.6.2.1
Ethernet Boot Data Formats
4.6.6.2.1.1
Limitations
4.6.6.2.1.2
BOOTP Request
4.6.6.2.1.2.1
MAC Header (DIX)
4.6.6.2.1.2.2
IPv4 Header
4.6.6.2.1.2.3
UDP Header
4.6.6.2.1.2.4
BOOTP Payload
4.6.6.2.1.2.5
TFTP
4.6.6.3
Ethernet Hand Over Process
4.6.7
USB Bootloader Operation
4.6.7.1
USB-Specific Attributes
4.6.7.1.1
DFU Device Mode
4.6.8
MMCSD Bootloader Operation
4.6.9
UART Bootloader Operation
4.6.9.1
Initialization Process
4.6.9.2
UART Loading Process
4.6.9.2.1
UART XMODEM
4.6.9.3
UART Hand-Over Process
4.7
Boot Memory Maps
4.7.1
Memory Layout/MPU
4.7.2
Global Memory Addresses Used by ROM Code
4.7.3
Memory Reserved by ROM Code
5
Device Configuration
5.1
Control Module (CTRL_MMR)
5.1.1
CTRL_MMR Overview
5.1.2
CTRL_MMR Functional Description
5.1.2.1
Register Partitions
5.1.2.2
Pad Configuration Registers
5.1.2.3
Kick Protection Registers
5.1.2.4
Proxy Addressing Registers
5.1.2.5
CTRL_MMR Interrupts
5.1.2.6
Inter-processor Communication Registers
5.1.2.7
Timer IO Muxing Control Registers
5.1.2.8
EHRPWM/EQEP Control and Status Registers
5.1.2.9
Clock Muxing and Division Registers
5.1.2.10
Module Control Registers
5.1.2.11
DDRSS Dynamic Frequency Change Registers
5.1.2.12
MAC Address Registers
5.1.2.13
Feature Registers
5.1.2.14
Power and Reset Related Registers
5.1.2.15
I/O Debounce Control Registers
5.1.3
Control Module Registers
5.2
Power
5.2.1
Power Management Overview
5.2.2
WKUP_PSC0 Device-Specific Information
5.2.3
Power Management Subsystems
5.2.3.1
POK, PRG_PP, and POR Modules
5.2.3.1.1
Power OK (POK) Modules
5.2.3.1.1.1
POK Overview
5.2.3.1.2
PoR/Reset Generator (PRG_PP) Modules
5.2.3.1.2.1
PRG / PRG_PP Overview
5.2.3.1.3
Power on Reset (POR) Module
5.2.3.1.3.1
POR Overview
5.2.3.1.4
Timing
5.2.3.1.5
Restrictions
5.2.3.1.6
PRG_PP Programming Model
5.2.3.2
Power Glitch Detect (PGD) Modules
5.2.3.3
Voltage and Thermal Manager (VTM)
5.2.3.3.1
VTM Overview
5.2.3.3.1.1
VTM Features
5.2.3.3.1.2
VTM Not Supported Features
5.2.3.3.2
VTM Functional Description
5.2.3.3.2.1
VTM Temperature Status and Thermal Management
5.2.3.3.2.1.1
10-bit Temperature Values Versus Temperature
5.2.3.3.2.2
VTM Temperature Driven Alerts and Interrupts
5.2.3.3.2.3
VTM ECC Aggregator
5.2.3.3.2.4
VTM Programming Model
5.2.3.3.2.4.1
VTM Maximum Temperature Outrange Alert
5.2.3.3.2.4.2
Sensors Programming Sequences
5.2.3.3.2.5
AVS-Class0
5.2.4
Dynamic Power Management
5.2.4.1
AVS Support
5.3
Reset
5.3.1
Reset Overview
5.3.2
Reset Modules
5.3.3
Reset Sources
5.3.4
Reset Status
5.3.5
Reset Control
5.3.6
BOOTMODE Pins
5.3.7
Reset Sequences
5.3.7.1
MCU_PORz Overview
5.3.7.2
MCU_PORz Sequence
5.3.7.3
MCU_RESETz Sequence
5.3.7.4
PORz Sequence
5.3.7.5
RESET_REQz Sequence
5.3.8
PLL Behavior on Reset
5.4
Clocking
5.4.1
Clocking Overview
5.4.2
Modules Controlled by PLL
5.4.3
Clock Mapping
5.4.4
Clock Inputs
5.4.4.1
Overview
5.4.4.2
Mapping of Clock Inputs
5.4.5
Clock Outputs
5.4.5.1
Observation Clock Pins
5.4.5.1.1
MCU_OBSCLK0 Pin
5.4.5.1.2
OBSCLK0, OBSCLK1, and OBSCLK2 Pins
5.4.5.2
System Clock Pins
5.4.5.2.1
MCU_SYSCLKOUT0
5.4.5.2.2
SYSCLKOUT0
5.4.6
Device Oscillators
5.4.6.1
Device Oscillators Integration
5.4.6.1.1
Oscillators with External Crystal
5.4.6.1.2
Internal RC Oscillator
5.4.6.2
Oscillator Clock Loss Detection
5.4.7
PLLs
5.4.7.1
WKUP and MCU Domains PLL Overview
5.4.7.2
MAIN Domain PLLs Overview
5.4.7.3
PLL Reference Clocks
5.4.7.3.1
PLLs in MCU Domain
5.4.7.3.2
PLLs in MAIN Domain
5.4.7.4
Generic PLL Overview
5.4.7.4.1
PLLs Output Clocks Parameters
5.4.7.4.1.1
PLLs Input Clocks
5.4.7.4.1.2
PLL Output Clocks
5.4.7.4.1.2.1
PLLTS16FFCLAFRAC2 Type Output Clocks
5.4.7.4.1.2.2
PLL Lock
5.4.7.4.1.2.3
HSDIVIDER
5.4.7.4.1.2.4
ICG Module
5.4.7.4.1.2.5
PLL Power Down
5.4.7.4.1.2.6
PLL Calibration
5.4.7.4.2
PLL Spread Spectrum Modulation Module
5.4.7.4.2.1
Definition of SSMOD
5.4.7.4.2.2
SSMOD Configuration
5.4.7.5
PLLs Device-Specific Information
5.4.7.5.1
SSMOD Related Bitfields Table
5.4.7.5.2
Clock Synthesis Inputs to the PLLs
5.4.7.5.3
Clock Output Parameter
5.4.7.5.4
Calibration Related Bitfields
5.4.7.6
PLL and PLL Controller Connection
5.4.7.7
System Clocks Operating Frequency Ranges
5.4.7.8
Recommended Clock and Control Signal Transition Behavior
5.4.7.9
Interface Clock Specifications
5.4.7.10
PLL, PLLCTRL, and HSDIV Controllers Programming Guide
5.4.7.10.1
PLL Initialization
5.4.7.10.1.1
Kick Protection Mechanism
5.4.7.10.1.2
PLL Initialization to PLL Mode
5.4.7.10.1.3
PLL Programming Requirements
5.4.7.10.1.3.1
PLL Calibration Procedure
5.4.7.10.2
Entire Sequence for Programming PLLCTRL, HSDIV, and PLL
5.5
Module Integration
5.5.1
ADC
5.5.1.1
ADC Unsupported Features
5.5.1.2
ADC Integration Details
5.5.2
ATL
5.5.2.1
ATL Unsupported Features
5.5.2.2
ATL Integration Details
5.5.3
CPSW2G
5.5.3.1
CPSW2G Unsupported Features
5.5.3.2
MCU_CPSW2G0 Integration Details
5.5.3.3
CPSW2G0 Integration Details
5.5.4
CSI_RX
5.5.4.1
CSI_RX Unsupported Features
5.5.4.2
CSI_RX Integration Details
5.5.5
CSI_TX
5.5.5.1
CSI_TX Unsupported Features
5.5.5.2
CSI_TX Integration Details
5.5.6
DCC
5.5.6.1
DCC Unsupported Features
5.5.6.2
DCC Integration Details
5.5.7
DMTIMER (Timer)
5.5.7.1
DMTIMER (Timer) Unsupported Features
5.5.7.2
DMTIMER (Timer) Integration Details
5.5.8
DPHY_RX
5.5.8.1
DPHY_RX Unsupported Features
5.5.8.2
DPHY_RX Integration Details
5.5.9
DPHY_TX
5.5.9.1
DPHY_TX Unsupported Features
5.5.9.2
DPHY_TX Integration Details
5.5.10
DSS/DSI
5.5.10.1
DSS Unsupported Features
5.5.10.2
DSI Unsupported Features
5.5.10.3
DSS/DSI Integration Details
5.5.10.3.1
DSS Pixel Clock Sourcing
5.5.11
eCAP
5.5.11.1
eCAP Unsupported Features
5.5.11.2
eCAP Integration Details
5.5.12
ePWM
5.5.12.1
ePWM Unsupported Features
5.5.12.2
ePWM Integration Details
5.5.13
ESM
5.5.13.1
ESM Unsupported Features
5.5.13.2
ESM Integration Details
5.5.14
FSS
5.5.14.1
FSS Unsupported Features
5.5.14.2
FSS Integration Details
5.5.15
GPIO
5.5.15.1
GPIO Unsupported Features
5.5.15.2
GPIO Integration Details
5.5.16
GPMC
5.5.16.1
GPMC Unsupported Features
5.5.16.2
GPMC Integration Details
5.5.17
GPU
5.5.17.1
GPU Unsupported Features
5.5.17.2
GPU Integration Details
5.5.18
I2C
5.5.18.1
WKUP_I2C0 Unsupported Features
5.5.18.2
MCU_I2C[1:0] Unsupported Features
5.5.18.3
I2C[6:0] Unsupported Features
5.5.18.4
I2C Integration Details
5.5.19
I3C
5.5.19.1
I3C Unsupported Features
5.5.19.2
I3C Integration Details
5.5.20
MCAN
5.5.20.1
MCAN Unsupported Features
5.5.20.2
MCAN Integration Details
5.5.21
MMCSD
5.5.21.1
MMCSD Unsupported Features
5.5.21.2
MMCSD Integration Details
5.5.22
McASP
5.5.22.1
McASP Unsupported Features
5.5.22.2
McASP Integration Details
5.5.23
McSPI
5.5.23.1
MCSPI Unsupported Features
5.5.23.2
MCSPI Integration Details
5.5.24
Navigator Subsystem (NAVSS)
5.5.24.1
Module Allocations
5.5.24.2
Main Navigator SubSystem (NAVSS)
5.5.24.2.1
Global Event Map (All NavSS)
5.5.24.2.2
PSIL System Thread Map (All NAVSS)
5.5.24.2.3
VBUSM Route ID Table
5.5.24.2.4
NAVSS Interrupt Router Configuration
5.5.24.2.5
NAVSS Ring Accelerator Configuration
5.5.24.3
MCU Navigator Subsystem (MCU NAVSS)
5.5.24.3.1
Global Event Map
5.5.24.3.2
PSIL System Thread Map (All NAVSS)
5.5.24.3.3
MCU NAVSS VBUSM Route ID Table
5.5.24.3.4
MCU NAVSS Interrupt Router Configuration
5.5.24.3.5
MCU NAVSS UDMASS Interrupt Aggregator Configuration
5.5.24.3.6
MCU NAVSS UDMA Configuration
5.5.24.3.7
MCU NAVSS Ring Accelerator Configuration
5.5.24.3.8
MCU NAVSS Proxy Configuration
5.5.24.3.9
MCU NAVSS Secure Proxy Configuration
5.5.24.4
Block Copy DMA (BCDMA)
5.5.24.4.1
Features Not Supported
5.5.24.4.2
Module Allocations
5.5.24.4.3
BCDMA Configuration
5.5.25
PCIE
5.5.25.1
PCIE Unsupported Features
5.5.25.2
PCIE Integration Details
5.5.26
R5FSS
5.5.26.1
R5FSS and MCU_R5FSS Unsupported Features
5.5.26.2
MCU_R5FSS Integration Details
5.5.26.3
R5FSS Integration Details
5.5.27
RAT
5.5.27.1
RAT Integration Details
5.5.27.1.1
RAT Source IDs
5.5.28
RTI
5.5.28.1
RTI Unsupported Features
5.5.28.2
RTI Integration Details
5.5.29
UART
5.5.29.1
UART Unsupported Features
5.5.29.2
UART Integration Details
5.5.30
USBSS
5.5.30.1
USB Unsupported Features
5.5.30.2
USB Integration Details
5.5.31
Video CODEC
5.5.31.1
CODEC Unsupported Features
5.5.31.2
CODEC Integration Details
5.5.32
VPAC
5.5.32.1
VPAC Unsupported Features
5.5.32.2
VPAC Integration Details
6
Processors and Accelerators
6.1
Compute Cluster
6.1.1
Compute Cluster Overview
6.2
Dual-A72 MPU Subsystem
6.2.1
A72SS Overview
6.2.1.1
A72SS Introduction
6.2.1.2
A72SS Features
6.2.2
A72SS Functional Description
6.2.2.1
A72SS Block Diagram
6.2.2.2
A72SS A72 Cluster
6.2.2.3
A72SS Interfaces and Async Bridges
6.2.2.4
A72SS Interrupts
6.2.2.4.1
A72SS Interrupt Inputs
6.2.2.4.2
A72SS Interrupt Outputs
6.2.2.5
A72SS Power Management, Clocking and Reset
6.2.2.5.1
A72SS Power Management
6.2.2.5.2
A72SS Clocking
6.2.2.6
A72SS Debug Support
6.2.2.7
A72SS Timestamps
6.2.2.8
A72SS Watchdog
6.2.2.9
A72SS Internal Diagnostics
6.2.2.9.1
A72SS ECC Aggregators During Low Power States
6.2.2.9.2
A72SS CBASS Diagnostics
6.2.2.9.3
A72SS SRAM Diagnostics
6.2.2.9.4
A72SS SRAM ECC Aggregator Configurations
6.2.2.10
A72SS Cache Pre-Warming
6.2.2.11
A72SS Boot
6.2.2.12
A72SS IPC with Other CPUs
6.3
Dual-R5F MCU Subsystem
6.3.1
R5FSS Overview
6.3.1.1
R5FSS Features
6.3.1.2
R5FSS Ports
6.3.2
R5FSS Functional Description
6.3.2.1
R5FSS Block Diagram
6.3.2.2
R5FSS Cortex-R5F Core
6.3.2.2.1
L1 Caches
6.3.2.2.2
Tightly-Coupled Memories (TCMs)
6.3.2.2.3
R5FSS Special Signals
6.3.2.3
R5FSS Interfaces
6.3.2.3.1
R5FSS Master Interfaces
6.3.2.3.2
R5FSS Slave Interfaces
6.3.2.4
R5FSS Power, Clocking and Reset
6.3.2.4.1
R5FSS Power
6.3.2.4.2
R5FSS Clocking
6.3.2.4.2.1
Changing MCU_R5FSS0 CPU Clock Frequency
6.3.2.4.3
R5FSS Reset
6.3.2.5
R5FSS Lockstep Error Detection Logic
6.3.2.5.1
CPU Output Compare Block
6.3.2.5.1.1
Operating Modes
6.3.2.5.1.2
Compare Block Active Mode
6.3.2.5.1.3
Self Test Mode
6.3.2.5.1.4
Compare Match Test
6.3.2.5.1.5
Compare Mismatch Test
6.3.2.5.1.6
Error Forcing Mode
6.3.2.5.1.7
Self Test Error Forcing Mode
6.3.2.5.2
Inactivity Monitor Block
6.3.2.5.2.1
Operating Modes
6.3.2.5.2.2
Compare Block Active Mode
6.3.2.5.2.3
Self Test Mode
6.3.2.5.2.4
Compare Match Test
6.3.2.5.2.5
Compare Mismatch Test
6.3.2.5.2.6
Error Forcing Mode
6.3.2.5.2.7
Self Test Error Forcing Mode
6.3.2.5.3
Polarity Inversion Logic
6.3.2.6
R5FSS Vectored Interrupt Manager (VIM)
6.3.2.6.1
VIM Overview
6.3.2.6.2
VIM Interrupt Inputs
6.3.2.6.3
VIM Interrupt Outputs
6.3.2.6.4
VIM Interrupt Vector Table (VIM RAM)
6.3.2.6.5
VIM Interrupt Prioritization
6.3.2.6.6
VIM ECC Support
6.3.2.6.7
VIM Lockstep Mode
6.3.2.6.8
VIM IDLE State
6.3.2.6.9
VIM Interrupt Handling
6.3.2.6.9.1
Servicing IRQ Through Vector Interface
6.3.2.6.9.2
Servicing IRQ Through MMR Interface
6.3.2.6.9.3
Servicing IRQ Through MMR Interface (Alternative)
6.3.2.6.9.4
Servicing FIQ
6.3.2.6.9.5
Servicing FIQ (Alternative)
6.3.2.7
R5FSS Region Address Translation (RAT)
6.3.2.7.1
RAT Overview
6.3.2.7.2
RAT Operation
6.3.2.7.3
RAT Error Logging
6.3.2.7.4
RAT Protection
6.3.2.8
R5FSS ECC Support
6.3.2.9
R5FSS Memory View
6.3.2.10
R5FSS Debug and Trace
6.3.2.11
R5FSS Boot Options
6.3.2.12
R5FSS Core Memory ECC Events
6.3.2.13
R5FSS_VIM Registers
6.3.2.14
R5FSS_RAT Registers
6.4
C71x DSP Subsystem
6.4.1
C71SS Overview
6.4.1.1
C71SS Features
6.4.2
C71SS Functional Description
6.4.2.1
C71x DSP CPU
6.4.2.2
C71x DSP Matrix Multiply Accelerator
6.4.2.3
C71x DSP Cache Memory System
6.4.2.3.1
C71x DSP L1 Program Memory
6.4.2.3.2
C71x DSP L1 Data Memory
6.4.2.3.3
C71x DSP L2 Memory
6.4.2.4
C71x DSP Streaming Engine
6.4.2.5
C71x DSP CorePac Memory Management Unit
6.4.2.6
C71x DSP ECC Support
6.4.2.7
C71x DSP Boot Configuration
6.4.2.8
C71x DSP Power-Up/Down Sequences
6.4.2.9
C71x DSP Interrupt Control
6.5
Graphics Accelerator (GPU)
6.5.1
GPU Overview
6.5.2
Features Supported
6.6
Video Accelerator
6.6.1
Introduction
6.6.2
Features
6.6.2.1
Performance
6.6.2.2
Codec Related Features
6.6.2.3
Non-Codec Related Features
6.6.3
Block Diagram
6.7
Vision Pre-processing Accelerator (VPAC)
6.7.1
VPAC Overview
6.7.1.1
VPAC Features
6.7.2
VPAC Subsystem Level
6.7.2.1
VPAC Subsystem Block Diagram
6.7.2.1.1
Notes on VISS RFE H3A Usage
6.7.2.2
VPAC Subsystem Clocks
6.7.2.3
VPAC Subsystem Resets
6.7.2.4
VPAC Subsystem Interrupts
6.7.2.5
VPAC Subsystem SL2 Memory Infrastructure
6.7.2.6
VPAC Subsystem DMA Infrastructure
6.7.2.7
VPAC Subsystem Data Routing Interconnect
6.7.2.8
VPAC Subsystem Pipeline Flow Control and Messaging
6.7.2.8.1
VISS Node Scheduler
6.7.2.8.2
LDC Node Scheduler
6.7.2.8.3
MSC Node Scheduler
6.7.2.8.4
NF Node Scheduler
6.7.2.8.5
Spare Scheduler
6.7.2.9
VPAC Subsystem Data Formats Support
6.7.2.10
VPAC Subsystem Debug Features
6.7.2.11
VPAC Subsystem Internal Diagnostic Features
6.7.2.11.1
Parallel Signature Analysis (PSA)
6.7.2.12
VPAC Subsystem Security Features
6.7.2.13
VPAC Subsystem Programmer’s Guide
6.7.2.13.1
Initialization Sequence
6.7.2.13.2
VISS Configuration
6.7.2.13.2.1
VISS UTC Configuration
6.7.2.13.2.2
VISS HTS Configuration for Line Mode
6.7.2.13.2.3
VISS HTS Configuration for Frame Mode
6.7.2.13.3
VISS OTF Configuration
6.7.2.13.4
LDC Configuration (LDC Connected to MSC0, NF and DMA)
6.7.2.13.4.1
LDC DMA Configuration
6.7.2.13.4.2
LDC HTS Configuration
6.7.2.13.5
Real-time Operating Requirements
6.7.3
VPAC Vision Imaging Subsystem (VISS)
6.7.3.1
VISS Top Level
6.7.3.1.1
Features Supported
6.7.3.1.2
VISS Block Diagram
6.7.3.1.3
VISS Data Flow within VPAC
6.7.3.1.3.1
VISS On-the-fly Processing
6.7.3.1.3.1.1
Non-WDR or Companded WDR Sensors
6.7.3.1.3.2
VISS Memory to Memory Image Processing
6.7.3.1.4
Concurret Machine Vision and Human Vision Output
6.7.3.1.5
VISS Clocking
6.7.3.1.6
VISS Data Formats Support
6.7.3.1.7
VISS VPORT Interface
6.7.3.1.8
VISS Submodule Integration Specifics
6.7.3.1.8.1
LSE Integration
6.7.3.1.8.2
Chromatic Aberration Correction
6.7.3.1.8.3
Spatial Noise Filter (NSF4V)
6.7.3.1.8.4
GLBCE Integration
6.7.3.1.8.4.1
GLBCE Startup
6.7.3.1.8.4.2
GLBCE Bypass
6.7.3.1.8.5
Flexible Color Processing (FCP)
6.7.3.1.9
VISS Stall Handling
6.7.3.1.10
VISS Blanking Requirements
6.7.3.1.11
FCP2 Sync FIFO
6.7.3.1.12
VISS Interrupts
6.7.3.1.12.1
Interrupts Merging
6.7.3.1.12.2
Handling of Configuration Error Interrupts
6.7.3.1.13
VISS Error Correcting Code (ECC) Support
6.7.3.1.14
VISS Programmer's Guide
6.7.3.1.14.1
VISS Initialization Sequence
6.7.3.1.14.2
VISS Configuration Restrictions
6.7.3.1.14.3
VISS Real-time Operating Requirements
6.7.3.2
VISS RAW Frond-End (RAWFE)
6.7.3.2.1
RAWFE Overview
6.7.3.2.1.1
RAWFE Supported Features
6.7.3.2.1.2
RAWFE Not Supported Features
6.7.3.2.2
RAWFE Functional Description
6.7.3.2.2.1
RAWFE Functional Operation
6.7.3.2.2.2
RAWFE Integration in VISS
6.7.3.2.2.3
RAWFE Memory Map
6.7.3.2.2.4
RAWFE ECC for RAMs
6.7.3.2.3
RAWFE Interrupts
6.7.3.2.3.1
RAWFE CPU Interrupts
6.7.3.2.3.2
RAWFE Debug Events
6.7.3.2.3.3
RAWFE Interrupt Handling: High Priority
6.7.3.2.3.4
RAWFE Interrupt Handling: Low Priority
6.7.3.2.4
RAWFE Sub-Modules Details
6.7.3.2.4.1
RAWFE Decompanding Block
6.7.3.2.4.1.1
RAWFE Mask & Shift
6.7.3.2.4.1.2
RAWFE Piece Wise Linear Operation
6.7.3.2.4.1.3
RAWFE Offset/WB-1 Block
6.7.3.2.4.1.4
RAWFE LUT Based compression
6.7.3.2.4.2
RAWFE WDR Merge Block
6.7.3.2.4.2.1
RAWFE WDR Motion Adaptive Merge (MA1 / MA2)
6.7.3.2.4.2.2
RAWFE Companding LUT
6.7.3.2.4.3
RAWFE Defective Pixel Correction (DPC) Block
6.7.3.2.4.3.1
RAWFE LUT Based DPC
6.7.3.2.4.3.2
RAWFE On-The-Fly (OTF) DPC
6.7.3.2.4.4
RAWFE Lens Shading Correction (LSC) and Digital Gain (DG) Block
6.7.3.2.4.4.1
RAWFE LSC Features Supported
6.7.3.2.4.4.2
RAWFE LSC Image Framing with Respect to Gain Map Samples
6.7.3.2.4.5
RAWFE Gain & Offset Block
6.7.3.2.4.6
RAWFE H3A
6.7.3.2.4.6.1
RAWFE H3A Overview
6.7.3.2.4.6.2
RAWFE H3A Top-Level Block Diagram
6.7.3.2.4.6.3
RAWFE H3A Line Framing Logic
6.7.3.2.4.6.4
RAWFE H3A Optional Preprocessing
6.7.3.2.4.6.5
RAWFE H3A Autofocus Engine
6.7.3.2.4.6.5.1
RAWFE H3A Paxel Extraction
6.7.3.2.4.6.5.2
RAWFE H3A Horizontal FV Calculator
6.7.3.2.4.6.5.3
RAWFE H3A HFV Accumulator
6.7.3.2.4.6.5.4
RAWFE H3A VFV Calculator
6.7.3.2.4.6.5.5
RAWFE H3A VFV Accumulator
6.7.3.2.4.6.6
RAWFE H3A AE/AWB Engine
6.7.3.2.4.6.6.1
RAWFE H3A Subsampler
6.7.3.2.4.6.6.2
RAWFE H3A Additional Black Row of AE/AWB Windows
6.7.3.2.4.6.6.3
RAWFE H3A Saturation Check
6.7.3.2.4.6.6.4
RAWFE H3A AE/AWB Accumulators
6.7.3.2.4.6.7
RAWFE H3A DMA Interface
6.7.3.2.4.6.8
RAWFE H3A Events and Status Checking
6.7.3.2.4.6.9
RAWFE H3A Interface Mux
6.7.3.2.4.6.10
RAWFE H3A interface to LSE
6.7.3.2.4.6.11
RAWFE H3A Erratas
6.7.3.2.5
RAWFE Programmer’s Guide
6.7.3.2.5.1
RAWFE Core programming details
6.7.3.2.5.2
RAWFE HTS programming details
6.7.3.2.5.3
RAWFE Data transfer programming details
6.7.3.2.5.4
RAWFE Initialization Sequence
6.7.3.2.5.5
RAWFE Real-time Оperating Requirements
6.7.3.2.5.6
RAWFE Power up/down Sequence
6.7.3.3
Chromatic Aberration Correction (CAC) Module
6.7.3.3.1
Overview and Feature List
6.7.3.3.1.1
Features Supported
6.7.3.3.2
Functional Description
6.7.3.3.2.1
CAC Integration in VISS
6.7.3.3.2.2
Introduction
6.7.3.3.2.3
Functional Operation
6.7.3.3.2.3.1
CAC Back Mapping
6.7.3.3.2.3.1.1
Offset Table Storage Format
6.7.3.3.2.3.2
Pixel Interpolation
6.7.3.3.2.3.3
Bi-cubic Coefficients
6.7.3.3.2.4
Interrupt Conditions
6.7.3.3.2.4.1
Interrupts
6.7.3.3.2.4.2
Debug Events
6.7.3.4
VISS Spatial Noise Filter (NSF4V)
6.7.3.4.1
NSF4V Introduction
6.7.3.4.1.1
NSF4V Features
6.7.3.4.2
NSF4V Overview
6.7.3.4.2.1
Decomposition Kernel Representation
6.7.3.4.3
NSF4V Lens Shading Correction Compensation
6.7.3.4.4
NSF4V Noise Threshold Adaptation to Local Image Intensity
6.7.3.4.5
Delta Features
6.7.3.5
VISS Global/Local Brightness and Contrast Enhancement (GLBCE) Module
6.7.3.5.1
GLBCE Overview
6.7.3.5.2
GLBCE Interface
6.7.3.5.3
GLBCE Core
6.7.3.5.3.1
GLBCE Core Key Parameters
6.7.3.5.3.2
GLBCE Iridix Strength Calculation
6.7.3.5.3.3
GLBCE Iridix Configuration Registers
6.7.3.5.3.3.1
GLBCE Iridix Frame Width
6.7.3.5.3.3.2
GLBCE Iridix Frame Height
6.7.3.5.3.3.3
GLBCE Iridix Control 0
6.7.3.5.3.3.4
GLBCE Iridix Control 1
6.7.3.5.3.3.5
GLBCE Iridix Strength
6.7.3.5.3.3.6
GLBCE Iridix Variance
6.7.3.5.3.3.7
GLBCE Iridix Dither
6.7.3.5.3.3.8
GLBCE Iridix Amplification Limit
6.7.3.5.3.3.9
GLBCE Iridix Slope Min and Max
6.7.3.5.3.3.10
GLBCE Iridix Black Level
6.7.3.5.3.3.11
GLBCE Iridix White Level
6.7.3.5.3.3.12
GLBCE Iridix Asymmetry Function Look-up-table
6.7.3.5.3.3.13
GLBCE Iridix Forward and Reverse Perceptual Functions Look-up-tables
6.7.3.5.3.3.14
GLBCE Iridix WDR Look-up-table
6.7.3.5.4
GLBCE Embedded Memory
6.7.3.5.5
GLBCE General Processing
6.7.3.5.6
GLBCE Continuous Frame Processing
6.7.3.5.7
GLBCE Single Image Processing
6.7.3.6
VISS Flexible Color Processing (FCP) Module
6.7.3.6.1
FCP Overview
6.7.3.6.1.1
FCP Features Supported
6.7.3.6.2
FCP Functional Description
6.7.3.6.3
FCP Submodule Details
6.7.3.6.3.1
Flexible CFA / Demosaicing
6.7.3.6.3.1.1
Feature-set
6.7.3.6.3.1.2
Block Diagram of Flexible CFA
6.7.3.6.3.1.2.1
Gradient/Threshold Calculation
6.7.3.6.3.1.2.2
Software Controlled Direction Selection
6.7.3.6.3.1.3
Example Filter Coefficients - Green Interpolation
6.7.3.6.3.1.3.1
Example Filter Coefficients - Red/Blue Interpolation
6.7.3.6.3.1.4
CFA 16-Bit Upgrade
6.7.3.6.3.1.5
FIR Filter Output Scaling
6.7.3.6.3.1.6
Decopanding, 24-bit Color Conversion Matrix and Companding Blocks
6.7.3.6.3.1.6.1
The DcmpdLUT Block
6.7.3.6.3.1.6.2
The CCM Block
6.7.3.6.3.1.6.3
The CmpdLUT Block
6.7.3.6.3.1.6.4
Controls for the Decompanding, CCM, and Companding Blocks
6.7.3.6.3.1.6.5
Example Use Cases
6.7.3.6.3.2
Edge Enhancer Module Wrapper (WEE)
6.7.3.6.3.2.1
Align 12 Block
6.7.3.6.3.2.2
Align 8 Block
6.7.3.6.3.2.3
Mux Blocks
6.7.3.6.3.2.4
SL - Shift Left Block
6.7.3.6.3.2.5
EE - Edge Enhancer Block
6.7.3.6.3.2.6
SR - Shift Right Block
6.7.3.6.3.2.7
Edge Enhancer Module Wrapper (WEE) Registers
6.7.3.6.3.3
Flexible Color Conversion (CC)
6.7.3.6.3.3.1
Interface Mux
6.7.3.6.3.3.2
Color Conversion (CCM-1)
6.7.3.6.3.3.3
RGB to HSX Conversion
6.7.3.6.3.3.3.1
Weighted Average Block
6.7.3.6.3.3.3.2
Saturation Block
6.7.3.6.3.3.3.3
Division Block
6.7.3.6.3.3.3.4
LUT Based 12 to 8 Downsampling
6.7.3.6.3.3.4
Histogram
6.7.3.6.3.3.5
Contrast Stretch / Gamma
6.7.3.6.3.3.6
RGB-YUV Conversion
6.7.3.6.3.4
444-422/420 Chroma Down-sampler
6.7.3.6.3.5
Blanking and Latency
6.7.3.6.4
FCP Clocking
6.7.3.6.5
FCP Interrupts
6.7.3.6.6
FCP Programmer’s Guide
6.7.3.6.6.1
HWA Core Programming Details
6.7.3.6.6.2
HWA HTS Programming Details
6.7.3.6.6.3
HWA Data Transfer Programming Details
6.7.3.6.6.4
Initialization Sequence
6.7.3.6.6.5
Real-time Operating Requirements
6.7.3.6.6.6
Power Up/Down Sequence
6.7.3.7
VISS Edge Enhancer (EE)
6.7.3.7.1
Edge Enhancer Introduction
6.7.3.7.1.1
Edge Enhancer Filter
6.7.3.7.1.2
Edge Sharpener Filter
6.7.3.7.1.3
Merge Block
6.7.3.7.2
Edge Enhancer Programming Model
6.7.4
VPAC Lens Distortion Correction (LDC) Module
6.7.4.1
LDC Overview
6.7.4.1.1
LDC Features
6.7.4.2
LDC Functional Description
6.7.4.2.1
LDC Integration in VPAC
6.7.4.2.2
LDC Block Diagram
6.7.4.2.3
LDC Clocks
6.7.4.2.4
LDC Interrupts
6.7.4.2.4.1
LDC Interrupt Events Description
6.7.4.2.4.1.1
PIX_IBLK_OUTOFBOUND
6.7.4.2.4.1.2
MESH_IBLK_OUTOFBOUND
6.7.4.2.4.1.3
IFR_OUTOFBOUND
6.7.4.2.4.1.4
INT_SZOVF
6.7.4.2.4.1.5
VPAC_LDC_FR_DONE_EVT
6.7.4.2.4.1.6
VPAC_LDC_SL2_WR_ERR
6.7.4.2.4.1.7
PIX_IBLK_MEMOVF
6.7.4.2.4.1.8
MESH_IBLK_MEMOVF
6.7.4.2.4.1.9
VPAC_LDC_VBUSM_RD_ERR
6.7.4.2.5
LDC Affine Transform
6.7.4.2.6
LDC Perspective Transformation
6.7.4.2.7
LDC Lens Distortion Back Mapping
6.7.4.2.7.1
LDC Mesh Table Storage Format
6.7.4.2.8
LDC Pixel Interpolation
6.7.4.2.9
LDC Buffer Management
6.7.4.2.9.1
LDC Buffer Management
6.7.4.2.10
LDC Multi Region with Variable Block size
6.7.4.2.10.1
LDC Region Skip Feature
6.7.4.2.10.2
LDC Support for sub-set of 3x3 regions
6.7.4.2.10.3
LDC Limitations of Multi Region Scheme
6.7.4.2.10.4
LDC Multi Region Block Constrains
6.7.4.2.11
LDC Multi-pass Frame processing
6.7.4.2.12
LDC Input/Output Data Formats
6.7.4.2.13
LDC YUV422 to YUV420 Conversion
6.7.4.2.14
Independent Channel Control
6.7.4.2.15
LDC SL2 Interface (LSE)
6.7.4.2.15.1
LDC PSA (Parallel Signature Analysis)
6.7.4.2.16
LDC LUT Mapped Dual Output
6.7.4.2.17
LDC Band Width Controller
6.7.4.2.18
LDC Input Block Fetch Limit
6.7.4.2.19
LDC HTS Interface
6.7.4.2.20
LDC VBUSM Read Interface
6.7.4.2.21
Partial Input Frame Storage
6.7.4.2.22
Hybrid Addressing
6.7.4.3
LDC Programmers Guide
6.7.4.3.1
LDC Programming Geometric Distortion Mode
6.7.4.3.2
LDC Programming Rotational Video Stabilization (Affine Transformation)
6.7.4.3.3
LDC Programming Perspective Transformation
6.7.4.3.4
LDC Programming LSE
6.7.4.3.5
LDC Programming Restrictions and Special Cases
6.7.5
VPAC Multi-Scaler (MSC)
6.7.5.1
MSC Overview
6.7.5.1.1
MSC Features
6.7.5.2
MSC Functional Description
6.7.5.2.1
MSC Functional Overview
6.7.5.2.2
Resizer Algorithm Details
6.7.5.2.2.1
Multiple Scales Generations
6.7.5.2.2.2
Polyphase Filter
6.7.5.2.2.2.1
Interpolation/Resampling
6.7.5.2.2.2.2
Phase Calculation and Re-sampler
6.7.5.2.2.2.3
Shared Coefficient Buffers
6.7.5.2.2.2.4
Border Pixel Padding
6.7.5.2.2.3
ROI Handling
6.7.5.2.3
MSC Data Formats Supported
6.7.5.3
MSC Interrupt Conditions
6.7.5.3.1
CPU Interrupts
6.7.5.3.2
Interrupt Event Description
6.7.5.3.2.1
VPAC_MSC_LSE_FR_DONE_EVT_0/1 Events
6.7.5.3.2.2
VPAC_MSC_LSE_SL2_RD_ERR Interrupt Event
6.7.5.3.2.3
VPAC_MSC_LSE_SL2_WR_ERR Interrupt Event
6.7.5.4
MSC Submodule Details
6.7.5.4.1
MSC Configuration Interface (MSC_CFG)
6.7.5.4.2
MSC Load Store Engine (MSC_LSE)
6.7.5.4.2.1
MSC_LSE Overview
6.7.5.4.2.1.1
MSC_LSE Features
6.7.5.4.2.2
MSC_LSE Internal Data Loopback Channel
6.7.5.4.2.3
MSC_LSE PSA Support
6.7.5.4.2.4
MSC_LSE Feature Detailed Description
6.7.5.4.3
MSC_CORE (HWA Core)
6.7.5.4.3.1
MSC_CORE Overview
6.7.5.4.3.2
Polyphase Filter of Vertical/Horizontal Resizers
6.7.5.4.3.2.1
Filter Data Path Logic
6.7.5.4.3.2.2
Filter Phase Calculation
6.7.5.4.3.2.3
Filter Parameters
6.7.5.4.3.2.4
Single-Phase Filter Parameters
6.7.5.4.3.2.5
Interleaved Mode Handling
6.7.5.4.3.2.6
Input Skip Line Support
6.7.5.4.3.3
Scaler Filter Thread Mapping
6.7.5.4.3.4
Filter Coefficients
6.7.5.4.3.4.1
Filter Coefficient Selection Algorithm
6.7.5.4.3.4.2
Filter Coefficient Parameter Configuration
6.7.5.4.3.4.3
3/4/5-Tap Filter Configuration
6.7.5.4.3.5
Input/Output ROI Trimmers
6.7.5.5
MSC Performance
6.7.5.6
MSC Clocking
6.7.5.7
MSC Reset
6.7.5.8
MSC Programmer’s Guide
6.7.5.8.1
Programming Model
6.7.5.8.1.1
MSC Programming Guidelines
6.7.5.8.1.2
MSC_Core Programming Details
6.7.5.8.1.3
MSC_LSE Programming Details
6.7.5.8.1.3.1
Input Thread Configuration:
6.7.5.8.1.3.2
Output Channel Configuration
6.7.5.8.1.4
MSC HTS Programming Details
6.7.5.8.1.5
MSC Data Transfer Programming Details
6.7.5.8.1.6
LSE Interrupt Programming
6.7.5.8.2
Initialization Sequence
6.7.5.8.3
Real-Time Operating Requirements
6.7.5.8.4
Power Up/Down Sequence
6.7.6
VPAC Noise Filter (NF)
6.7.6.1
NF Overview
6.7.6.1.1
NF Supported Features
6.7.6.1.2
NF Not Supported Features
6.7.6.2
NF Functional Description
6.7.6.2.1
Functional Operation
6.7.6.2.1.1
Overview
6.7.6.2.1.2
NF Integration In VPAC
6.7.6.2.1.3
Algorithm Details
6.7.6.2.1.4
Data Format Support In VPAC
6.7.6.3
NF Interrupts
6.7.6.3.1
CPU Interrupts
6.7.6.3.2
Interrupt Event Description
6.7.6.3.2.1
NF_FRAME_DONE Event
6.7.6.3.2.2
NF_SL2_READ_ERROR Event
6.7.6.3.2.3
NF_SL2_WRITE_ERROR Event
6.7.6.4
NF Submodule Details
6.7.6.4.1
NF_CFG
6.7.6.4.1.1
VBUSP Configuration Interface
6.7.6.4.1.2
Configuration Register Address Map
6.7.6.4.2
NF_LSE
6.7.6.4.2.1
NF_LSE Overview
6.7.6.4.2.2
NF_LSE Feature Detailed Description
6.7.6.4.3
HTS Interface And Integration
6.7.6.4.3.1
Hardware Thread Scheduler (HTS)
6.7.6.4.3.2
Synchronization With HTS
6.7.6.4.4
Noise Filter Core Block Diagram
6.7.6.4.4.1
VP Port (NF_LSE To/From NF_CORE Over VBUSP Interface)
6.7.6.4.4.2
Space Weight Details
6.7.6.4.4.3
Weight Calculation Logic
6.7.6.4.4.3.1
Combined LUT For Space And Range Weights
6.7.6.4.4.4
Reciprocal Calculation Logic
6.7.6.4.4.5
Border Handling
6.7.6.4.4.5.1
Border Handling (Simple)
6.7.6.4.5
Usage As Generic 2D Filter Engine
6.7.6.4.6
Adaptive Bilateral Weight Support
6.7.6.4.7
Chroma Handling (Interleaved Mode)
6.7.6.5
NF Integration Details
6.7.6.5.1
Performance Requirements
6.7.6.5.2
Slave VBUSP Interface Clock
6.7.6.5.3
Clocking
6.7.6.6
NF Programmer’s Guide
6.7.6.6.1
Programming Model
6.7.6.6.1.1
HWA Core Programming Details
6.7.6.6.1.2
NF SL2 Wrapper Interface Programming Details
6.7.6.6.1.3
HWA HTS Programming Details
6.7.6.6.1.4
HWA Data Transfer Programming Details
6.7.6.6.2
Initialization Sequence
6.7.6.6.3
Real-Time Operating Requirements
6.7.6.6.4
Power Up/Down Sequence
6.7.6.6.5
Clock Stop
6.8
Depth and Motion Perception Accelerator (DMPAC)
6.8.1
DMPAC Overview
6.8.1.1
DMPAC Features
7
Interprocessor Communication
7.1
Mailbox
7.1.1
Mailbox Overview
7.1.1.1
Mailbox Features
7.1.1.2
Mailbox Parameters
7.1.2
Mailbox Integration
7.1.2.1
System Mailbox Integration
7.1.3
Mailbox Functional Description
7.1.3.1
Mailbox Block Diagram
7.1.3.2
Mailbox Software Reset
7.1.3.3
Mailbox Power Management
7.1.3.4
Mailbox Interrupt Requests
7.1.3.5
Mailbox Assignment
7.1.3.5.1
Description
7.1.3.6
Sending and Receiving Messages
7.1.3.6.1
Description
7.1.3.7
Example of Communication
7.1.4
Mailbox Programming Guide
7.1.4.1
Mailbox Low-level Programming Models
7.1.4.1.1
Global Initialization
7.1.4.1.1.1
Surrounding Modules Global Initialization
7.1.4.1.1.2
Mailbox Global Initialization
7.1.4.1.1.2.1
Main Sequence - Mailbox Global Initialization
7.1.4.1.2
Mailbox Operational Modes Configuration
7.1.4.1.2.1
Mailbox Processing modes
7.1.4.1.2.1.1
Main Sequence - Sending a Message (Polling Method)
7.1.4.1.2.1.2
Main Sequence - Sending a Message (Interrupt Method)
7.1.4.1.2.1.3
Main Sequence - Receiving a Message (Polling Method)
7.1.4.1.2.1.4
Main Sequence - Receiving a Message (Interrupt Method)
7.1.4.1.3
Mailbox Events Servicing
7.1.4.1.3.1
Events Servicing in Sending Mode
7.1.4.1.3.2
Events Servicing in Receiving Mode
7.2
Spinlock
7.2.1
Spinlock Overview
7.2.2
Spinlock Functional Description
7.2.2.1
Spinlock Software Reset
7.2.2.2
Spinlock Power Management
7.2.2.3
About Spinlocks
7.2.2.4
Spinlock Functional Operation
7.2.3
Spinlock Programming Guide
7.2.3.1
Spinlock Low-level Programming Models
7.2.3.1.1
Basic Spinlock Operations
7.2.3.1.1.1
Spinlocks Clearing After a System Bug Recovery
7.2.3.1.1.2
Take and Release Spinlock
8
Memory Controllers
8.1
Multicore Shared Memory Controller (MSMC)
8.1.1
MSMC Overview
8.1.1.1
MSMC Not Supported Features
8.1.2
MSMC Functional Description
8.1.2.1
MSMC Block Diagram
8.1.2.2
MSMC On-Chip Memory Banking
8.1.2.3
MSMC Snoop Filter and Data Cache
8.1.2.3.1
Way Partitioning
8.1.2.3.2
Cache Size Configuration and Associativity
8.1.2.4
MSMC Access Protection Checks
8.1.2.5
MSMC Null Slave
8.1.2.6
MSMC Resource Arbitration
8.1.2.7
MSMC Error Detection and Correction
8.1.2.7.1
On-chip SRAM and Pipeline Data Protection
8.1.2.7.2
On-chip SRAM L3 Cache Tag and Snoop Filter Protection
8.1.2.7.3
On-chip SRAM Memory Mapped SRAM Snoop Filter Protection
8.1.2.7.4
Background Parity Refresh (Scrubbing)
8.1.2.8
MSMC Interrupts
8.1.2.8.1
Raw Interrupt Registers
8.1.2.8.2
Interrupt Enable Registers
8.1.2.8.3
Triggered and Enabled Interrupts
8.1.2.9
MSMC Memory Regions
8.1.2.10
MSMC Hardware Coherence
8.1.2.10.1
Snoop Filter Broadcast Mode
8.1.2.11
MSMC Quality-of-Service
8.1.2.12
MSMC Memory Regions Protection
8.1.2.13
MSMC Cache Tag View
8.1.2.14
MSMC R50+ Features
8.1.2.14.1
Way Group Partitioning
8.1.2.14.1.1
MMRs Related to Way Group Partitioning Feature
8.1.2.14.1.1.1
RT_WAY_SELECT [Address = 0x8000]
8.1.2.14.1.1.2
NRT_WAY_SELECT [Address = 0x8008]
8.1.2.14.2
Write Back Invalidate
8.1.2.14.2.1
MMR Related to Snoop Filter Invalidate Feature
8.1.2.14.2.1.1
WBINV_CTRL [Address = 0x4000]
8.1.2.14.3
FFI Support
8.1.2.14.3.1
FFI Event Sequence
8.1.2.14.4
Broadcast Mode
8.1.2.14.5
DRU and SDMA Access Constraints (Access ARC Removal)
8.1.2.14.6
EMIF Interleaving
8.1.2.14.7
QoS Fix/RT Hazarding
8.2
DDR Subsystem (DDRSS)
8.2.1
DDRSS Overview
8.2.2
DDRSS Environment
8.2.3
DDRSS Functional Description
8.2.3.1
DDRSS MSMC2DDR Bridge
8.2.3.1.1
VBUSM.C Threads
8.2.3.1.2
Class of Service (CoS)
8.2.3.1.3
AXI Write Data All-Strobes
8.2.3.1.4
Inline ECC for SDRAM Data
8.2.3.1.4.1
ECC Cache
8.2.3.1.4.2
ECC Statistics
8.2.3.1.5
Opcode Checking
8.2.3.1.6
Address Alias Prevention
8.2.3.1.7
Data Error Detection and Correction
8.2.3.1.8
AXI Bus Timeout
8.2.3.2
DDRSS Interrupts
8.2.3.3
DDRSS Memory Regions
8.2.3.4
DDRSS ECC Support
8.2.3.5
DDRSS Dynamic Frequency Change Interface
8.2.3.6
DDR Controller Functional Description
8.2.3.6.1
DDR PHY Interface (DFI)
8.2.3.6.2
Command Queue
8.2.3.6.2.1
Placement Logic
8.2.3.6.2.2
Command Selection Logic
8.2.3.6.3
Low Power Control
8.2.3.6.4
Transaction Processing
8.2.3.6.5
BIST Engine
8.2.3.6.6
ECC Engine
8.2.3.6.7
Address Mapping
8.2.3.6.8
Paging Policy
8.2.3.6.9
DDR Controller Initialization
8.2.3.6.10
Programming LPDDR4 Memories
8.2.3.6.10.1
Frequency Set Point (FSP)
8.2.3.6.10.1.1
FSP Mode Register Programming During Initialization
8.2.3.6.10.1.2
FSP Mode Register Programming During Normal Operation
8.2.3.6.10.1.3
FSP Mode Register Programming During Dynamic Frequency Scaling
8.2.3.6.10.2
Data Bus Inversion (DBI)
8.2.3.6.10.3
On-Die Termination
8.2.3.6.10.3.1
LPDDR4 DQ ODT
8.2.3.6.10.3.2
LPDDR4 CA ODT
8.2.3.6.10.4
Byte Lane Swapping
8.2.3.6.10.5
DQS Interval Oscillator
8.2.3.6.10.5.1
Oscillator State Machine
8.2.3.6.10.6
Per-Bank Refresh (PBR)
8.2.3.6.10.6.1
Normal Operation
8.2.3.6.10.6.2
Continuous Refresh Request Mode
8.2.3.7
DDR PHY Functional Description
8.2.3.7.1
Data Slice
8.2.3.7.2
Address Slice
8.2.3.7.2.1
Address Swapping
8.2.3.7.3
Address/Control Slice
8.2.3.7.4
Clock Slice
8.2.3.7.5
DDR PHY Initialization
8.2.3.7.6
DDR PHY Dynamic Frequency Scaling (DFS)
8.2.3.7.7
Chip Select and Frequency Based Register Settings
8.2.3.7.8
Low-Power Modes
8.2.3.7.9
Training Support
8.2.3.7.9.1
Write Leveling
8.2.3.7.9.2
Read Gate Training
8.2.3.7.9.3
Read Data Eye Training
8.2.3.7.9.4
Write DQ Training
8.2.3.7.9.5
CA Training
8.2.3.7.9.6
CS Training
8.2.3.7.10
Data Bus Inversion (DBI)
8.2.3.7.11
I/O Pad Calibration
8.2.3.7.12
DQS Error
8.2.3.8
PI Functional Description
8.2.3.8.1
PI Initialization
8.2.4
DDRSS Registers
8.3
Peripheral Virtualization Unit (PVU)
8.3.1
PVU Overview
8.3.1.1
PVU Features
8.3.1.2
PVU Parameters
8.3.2
PVU Functional Description
8.3.2.1
Functional Operation Overview
8.3.2.2
PVU Channels
8.3.2.3
TLB
8.3.2.4
TLB Entry
8.3.2.5
TLB Selection
8.3.2.6
DMA Classes
8.3.2.7
General virtIDs
8.3.2.8
TLB Lookup
8.3.2.9
TLB Miss
8.3.2.10
Multiple Matching Entries
8.3.2.11
TLB Disable
8.3.2.12
TLB Chaining
8.3.2.13
TLB Permissions
8.3.2.14
Translation
8.3.2.15
Memory Attributes
8.3.2.16
Faulted Transactions
8.3.2.17
Non-Virtual Transactions
8.3.2.18
Allowed virtIDs
8.3.2.19
Software Control
8.3.2.20
Fault Logging
8.3.2.21
Alignment Restrictions
8.4
Region-based Address Translation (RAT) Module
8.4.1
RAT Functional Description
8.4.1.1
RAT Operation
8.4.1.2
RAT Error Logging
9
Interrupts
9.1
Interrupt Architecture
9.2
Interrupt Controllers
9.2.1
Generic Interrupt Controller (GIC)
9.2.1.1
GIC Overview
9.2.1.1.1
GIC Features
9.2.1.1.2
GIC Not Supported Features
9.2.1.2
GIC Functional Description
9.2.1.2.1
Arm GIC-500
9.2.1.2.2
GIC Interrupt Types
9.2.1.2.3
GIC Interfaces
9.2.1.2.4
GIC Interrupt Outputs
9.2.1.2.5
GIC ECC Support
9.2.1.2.6
GIC AXI2VBUSM and VBUSM2AXI Bridges
9.2.2
Cluster Level Event Controller (CLEC)
9.2.2.1
CLEC Overview
9.2.2.2
CLEC Functional Description
9.2.2.2.1
CLEC Interrupt Event Routing
9.2.2.2.2
CLEC Virtualization, Isolation and Access Control
9.2.2.2.3
CLEC Memory Protection
9.2.2.2.4
CLEC ECC Support
9.2.2.2.5
CLEC Intra-Core Communication
9.2.2.2.6
CLEC Event Maps
9.2.2.2.6.1
CLEC ESM Event Routing
9.2.3
Other Interrupt Controllers
9.3
Interrupt Routers
9.3.1
INTRTR Overview
9.4
Interrupt Sources
10
Data Movement Architecture (DMA)
10.1
DMA Architecture
10.1.1
Overview
10.1.1.1
Navigator Subsystem
10.1.1.2
Ring Accelerator (RA)
10.1.1.3
Proxy
10.1.1.4
Secure Proxy
10.1.1.5
Interrupt Aggregator (INTA)
10.1.1.6
Interrupt Router (IR)
10.1.1.7
Unified DMA – Third Party Channel Controller (UDMA-C)
10.1.1.8
Unified Transfer Controller (UTC)
10.1.1.9
Data Routing Unit (DRU)
10.1.1.10
Unified DMA – Peripheral Root Complex (UDMA-P)
10.1.1.11
Peripheral DMA (PDMA)
10.1.1.12
Embedded DMA
10.1.1.13
Definition of Terms
10.1.2
DMA Hardware/Software Interface
10.1.2.1
Data Buffers
10.1.2.2
Descriptors
10.1.2.2.1
Host Packet Descriptor
10.1.2.2.2
Host Buffer Descriptor
10.1.2.2.3
Monolithic Packet Descriptor
10.1.2.2.4
Transfer Request Descriptor
10.1.2.3
Transfer Request Record
10.1.2.3.1
Overview
10.1.2.3.2
Addressing Algorithm
10.1.2.3.2.1
Linear Addressing (Forward)
10.1.2.3.3
Transfer Request Formats
10.1.2.3.4
Flags Field Definition
10.1.2.3.4.1
Type: TR Type Field
10.1.2.3.4.2
STATIC: Static Field Definition
10.1.2.3.4.3
EVENT_SIZE: Event Generation Definition
10.1.2.3.4.4
TRIGGER INFO: TR Triggers
10.1.2.3.4.5
TRIGGERX_TYPE: Trigger Type
10.1.2.3.4.6
TRIGGERX: Trigger Selection
10.1.2.3.4.7
CMD ID: Command ID Field Definition
10.1.2.3.4.8
Configuration Specific Flags Definition
10.1.2.3.5
TR Address and Size Attributes
10.1.2.3.5.1
ICNT0
10.1.2.3.5.2
ICNT1
10.1.2.3.5.3
ADDR
10.1.2.3.5.4
DIM1
10.1.2.3.5.5
ICNT2
10.1.2.3.5.6
ICNT3
10.1.2.3.5.7
DIM2
10.1.2.3.5.8
DIM3
10.1.2.3.5.9
DDIM1
10.1.2.3.5.10
DADDR
10.1.2.3.5.11
DDIM2
10.1.2.3.5.12
DDIM3
10.1.2.3.5.13
DICNT0
10.1.2.3.5.14
DICNT1
10.1.2.3.5.15
DICNT2
10.1.2.3.5.16
DICNT3
10.1.2.3.6
FMTFLAGS
10.1.2.3.6.1
AMODE: Addressing Mode Definition
10.1.2.3.6.1.1
Linear Addressing
10.1.2.3.6.1.2
Circular Addressing
10.1.2.3.6.2
DIR: Addressing Mode Direction Definition
10.1.2.3.6.3
ELTYPE: Element Type Definition
10.1.2.3.6.4
DFMT: Data Formatting Algorithm Definition
10.1.2.3.6.5
SECTR: Secondary Transfer Request Definition
10.1.2.3.6.5.1
Secondary TR Formats
10.1.2.3.6.5.2
Secondary TR FLAGS
10.1.2.3.6.5.2.1
SEC_TR_TYPE: Secondary TR Type Field
10.1.2.3.6.5.2.2
Multiple Buffer Interleave
10.1.2.3.6.6
AMODE SPECIFIC: Addressing Mode Field
10.1.2.3.6.6.1
Circular Address Mode Specific Flags
10.1.2.3.6.6.1.1
CBK0 and CBK1: Circular Block Size Selection
10.1.2.3.6.6.1.2
Amx: Addressing Mode Selection
10.1.2.3.6.7
Cache Flags
10.1.2.4
Transfer Response Record
10.1.2.4.1
STATUS Field Definition
10.1.2.4.1.1
STATUS_TYPE Definition
10.1.2.4.1.1.1
Transfer Error
10.1.2.4.1.1.2
Aborted Error
10.1.2.4.1.1.3
Submission Error
10.1.2.4.1.1.4
Unsupported Feature
10.1.2.4.1.1.5
Transfer Exception
10.1.2.4.1.1.6
Teardown Flush
10.1.2.5
Queues
10.1.2.5.1
Queue Types
10.1.2.5.1.1
Transmit Queues (Pass By Reference)
10.1.2.5.1.2
Transmit Queues (Pass By Value)
10.1.2.5.1.3
Transmit Completion Queues (Pass By Reference)
10.1.2.5.1.4
Transmit Completion Queues (Pass By Value)
10.1.2.5.1.5
Receive Queues
10.1.2.5.1.6
Free Descriptor Queues
10.1.2.5.1.7
Free Descriptor/Buffer Queues
10.1.2.5.2
Ring Accelerator Queues Implementation
10.1.3
Operational Description
10.1.3.1
Resource Allocation
10.1.3.2
Ring Accelerator Operation
10.1.3.2.1
Queue Initialization
10.1.3.2.2
Queuing packets (Exposed Ring Mode)
10.1.3.2.3
De-queuing packets (Exposed Ring Mode)
10.1.3.2.4
Queuing packets (Queue Mode)
10.1.3.2.5
De-queuing packets (Queue Mode)
10.1.3.3
UDMA Internal Transmit Channel Setup (All Packet Types)
10.1.3.4
UDMA Internal Transmit Channel Teardown (All Packet Types)
10.1.3.5
UDMA-P Transmit Channel Pause
10.1.3.6
UDMA-P Transmit Operation (Host Packet Type)
10.1.3.7
UDMA-P Transmit Operation (Monolithic Packet)
10.1.3.8
UDMA Transmit Operation (TR Packet)
10.1.3.9
UDMA Transmit Operation (Direct TR)
10.1.3.10
UDMA Transmit Error/Exception Handling
10.1.3.10.1
Null Icnt0 Error
10.1.3.10.2
Unsupported TR Type
10.1.3.10.3
Bus Errors
10.1.3.11
UDMA Receive Channel Setup (All Packet Types)
10.1.3.12
UDMA Receive Channel Teardown
10.1.3.13
UDMA-P Receive Channel Pause
10.1.3.14
UDMA-P Receive Free Descriptor/Buffer Queue Setup (Host Packets)
10.1.3.15
UDMA-P Receive FlowID Firewall Operation
10.1.3.16
UDMA-P Receive Operation (Host Packet)
10.1.3.17
UDMA-P Receive Operation (Monolithic Packet)
10.1.3.18
UDMA Receive Operation (TR Packet)
10.1.3.19
UDMA Receive Operation (Direct TR)
10.1.3.20
UDMA Receive Error/Exception Handling
10.1.3.20.1
Error Conditions
10.1.3.20.1.1
Bus Errors
10.1.3.20.1.2
Null Icnt0 Error
10.1.3.20.1.3
Unsupported TR Type
10.1.3.20.2
Exception Conditions Exception Conditions
10.1.3.20.2.1
Descriptor Starvation
10.1.3.20.2.2
Protocol Errors
10.1.3.20.2.3
Dropped Packets
10.1.3.20.2.4
Reception of EOL Delimiter
10.1.3.20.2.5
EOP Asserted Prematurely (Short Packet)
10.1.3.20.2.6
EOP Asserted Late (Long Packets)
10.1.3.21
UTC Operation
10.1.3.22
UTC Receive Error/Exception Handling
10.1.3.22.1
Error Handling
10.1.3.22.1.1
Null Icnt0 Error
10.1.3.22.1.2
Unsupported TR Type
10.1.3.22.2
Exception Conditions
10.1.3.22.2.1
Reception of EOL Delimiter
10.1.3.22.2.2
EOP Asserted Prematurely (Short Packet)
10.1.3.22.2.3
EOP Asserted Late (Long Packets)
10.2
Navigator Subsystem (NAVSS)
10.2.1
Main Navigator Subsystem (NAVSS)
10.2.1.1
NAVSS Overview
10.2.1.1.1
Main Navigator Subsystem (NAVSS) Ports
10.2.1.2
NAVSS Functional Description
10.2.1.3
NAVSS Interrupt Configuration
10.2.1.3.1
NAVSS Event and Interrupt Flow
10.2.1.3.1.1
NAVSS Interrupts Description
10.2.1.3.1.2
Application Example
10.2.2
MCU Navigator Subsystem (MCU NAVSS)
10.2.2.1
MCU NAVSS Overview
10.2.2.1.1
MCU NAVSS Ports
10.2.2.2
MCU NAVSS Functional Description
10.2.3
Unified DMA Controller (UDMA)
10.2.3.1
UDMA Overview
10.2.3.1.1
UDMA Features
10.2.3.1.2
UDMA Parameters
10.2.3.1.3
Unified DMA Controller (UDMA) Ports
10.2.3.2
UDMA Functional Description
10.2.3.2.1
Block Diagram
10.2.3.2.2
General Functionality
10.2.3.2.2.1
Operational States
10.2.3.2.2.2
Tx Channel Allocation
10.2.3.2.2.3
Rx Channel Allocation
10.2.3.2.2.4
Tx Teardown
10.2.3.2.2.5
Rx Teardown
10.2.3.2.2.6
Tx Clock Stop
10.2.3.2.2.7
Rx Clock Stop
10.2.3.2.2.8
Rx Thread Enables
10.2.3.2.2.9
Events
10.2.3.2.2.9.1
Local Event Inputs
10.2.3.2.2.9.2
Inbound Tx PSI-L Events
10.2.3.2.2.9.3
Outbound Rx PSI-L Events
10.2.3.2.2.10
Emulation Control
10.2.3.2.3
Packet Oriented Transmit Operation
10.2.3.2.3.1
Packet Mode VBUSM Master Interface Command ID Selection
10.2.3.2.4
Packet Oriented Receive Operation
10.2.3.2.4.1
Rx Packet Drop
10.2.3.2.4.2
Rx Starvation and the Starvation Timer
10.2.3.2.5
Third Party Mode Operation
10.2.3.2.5.1
Events and Flow Control
10.2.3.2.5.1.1
Channel Triggering
10.2.3.2.5.1.2
Internal TR Completion Events
10.2.3.2.5.2
Transmit Operation
10.2.3.2.5.2.1
Transfer Request
10.2.3.2.5.2.2
Transfer Response
10.2.3.2.5.2.3
Data Transfer
10.2.3.2.5.2.4
Memory Interface Transactions
10.2.3.2.5.2.5
Error Handling
10.2.3.2.5.3
Receive Operation
10.2.3.2.5.3.1
Transfer Request
10.2.3.2.5.3.2
Transfer Response
10.2.3.2.5.3.3
Error Handling
10.2.3.2.5.4
Data Transfer
10.2.3.2.5.4.1
Memory Interface Transactions
10.2.3.2.5.4.2
Rx Packet Drop
10.2.4
Ring Accelerator (RINGACC)
10.2.4.1
RINGACC Overview
10.2.4.1.1
RINGACC Features
10.2.4.1.2
RINGACC Parameters
10.2.4.1.3
Ring Accelerator (RINGACC) Ports
10.2.4.2
RINGACC Functional Description
10.2.4.2.1
Block Diagram
10.2.4.2.1.1
Configuration Registers
10.2.4.2.1.2
Source Command FIFO
10.2.4.2.1.3
Source Write Data FIFO
10.2.4.2.1.4
Source Read Data FIFO
10.2.4.2.1.5
Source Write Status FIFO
10.2.4.2.1.6
Main State Machine
10.2.4.2.1.7
Destination Command FIFO
10.2.4.2.1.8
Destination Write Data FIFO
10.2.4.2.1.9
Destination Read Data FIFO
10.2.4.2.1.10
Destination Write Status FIFO
10.2.4.2.2
RINGACC Functional Operation
10.2.4.2.2.1
Queue Modes
10.2.4.2.2.1.1
Ring Mode
10.2.4.2.2.1.2
Messaging Mode
10.2.4.2.2.1.3
Credentials Mode
10.2.4.2.2.1.4
Queue Manager Mode
10.2.4.2.2.1.5
Peek Support
10.2.4.2.2.1.6
Index Register Operation
10.2.4.2.2.2
VBUSM Slave Ring Operations
10.2.4.2.2.3
VBUSM Master Interface Command ID Selection
10.2.4.2.2.4
Ring Push Operation (VBUSM Write to Source Interface)
10.2.4.2.2.5
Ring Pop Operation (VBUSM Read from Source Interface)
10.2.4.2.2.6
Host Doorbell Access
10.2.4.2.2.7
Queue Push Operation (VBUSM Write to Source Interface)
10.2.4.2.2.8
Queue Pop Operation (VBUSM Read from Source Interface)
10.2.4.2.2.9
Mismatched Element Size Handling
10.2.4.2.3
Events
10.2.4.2.4
Bus Error Handling
10.2.4.2.5
Monitors
10.2.4.2.5.1
Threshold Monitor
10.2.4.2.5.2
Watermark Monitor
10.2.4.2.5.3
Starvation Monitor
10.2.4.2.5.4
Statistics Monitor
10.2.4.2.5.5
Overflow
10.2.4.2.5.6
Ring Update Port
10.2.4.2.5.7
Tracing
10.2.5
Proxy
10.2.5.1
Proxy Overview
10.2.5.1.1
Proxy Features
10.2.5.1.2
Proxy Parameters
10.2.5.1.3
Proxy Ports
10.2.5.2
Proxy Functional Description
10.2.5.2.1
Targets
10.2.5.2.1.1
Ring Accelerator
10.2.5.2.2
Proxy Sizes
10.2.5.2.3
Proxy Interleaving
10.2.5.2.4
Proxy Host States
10.2.5.2.5
Proxy Host Channel Selection
10.2.5.2.6
Proxy Host Access
10.2.5.2.6.1
Proxy Host Writes
10.2.5.2.6.2
Proxy Host Reads
10.2.5.2.7
Permission Inheritance
10.2.5.2.8
Buffer Size
10.2.5.2.9
Error Events
10.2.5.2.10
Debug Reads
10.2.6
Secure Proxy
10.2.6.1
Secure Proxy Overview
10.2.6.1.1
Secure Proxy Features
10.2.6.1.2
Secure Proxy Parameters
10.2.6.1.3
Secure Proxy Ports
10.2.6.2
Secure Proxy Functional Description
10.2.6.2.1
Targets
10.2.6.2.1.1
Ring Accelerator
10.2.6.2.2
Buffers
10.2.6.2.2.1
Proxy Credits
10.2.6.2.2.2
Proxy Private Word
10.2.6.2.2.3
Completion Byte
10.2.6.2.3
Proxy Thread Sizes
10.2.6.2.4
Proxy Thread Interleaving
10.2.6.2.5
Proxy States
10.2.6.2.6
Proxy Host Access
10.2.6.2.6.1
Proxy Host Writes
10.2.6.2.6.2
Proxy Host Reads
10.2.6.2.6.3
Buffer Accesses
10.2.6.2.6.4
Target Access
10.2.6.2.6.5
Error State
10.2.6.2.7
Permission Inheritance
10.2.6.2.8
Resource Association
10.2.6.2.9
Direction
10.2.6.2.10
Threshold Events
10.2.6.2.11
Error Events
10.2.6.2.12
Bus Errors and Credits
10.2.6.2.13
Debug
10.2.7
Interrupt Aggregator (INTR_AGGR)
10.2.7.1
INTR_AGGR Overview
10.2.7.1.1
INTR_AGGR Features
10.2.7.1.2
INTR_AGGR Parameters
10.2.7.1.3
Interrupt Aggregator (INTR_AGGR) Ports
10.2.7.2
INTR_AGGR Functional Description
10.2.7.2.1
Submodule Descriptions
10.2.7.2.1.1
Status/Mask Registers
10.2.7.2.1.2
Interrupt Mapping Block
10.2.7.2.1.3
Global Event Input (GEVI) Counters
10.2.7.2.1.4
Local Event Input (LEVI) to Global Event Conversion
10.2.7.2.1.5
Global Event Multicast
10.2.7.2.2
General Functionality
10.2.7.2.2.1
Event to Interrupt Bit Steering
10.2.7.2.2.2
Interrupt Status
10.2.7.2.2.3
Interrupt Masked Status
10.2.7.2.2.4
Enabling/Disabling Individual Interrupt Source Bits
10.2.7.2.2.5
Interrupt Output Generation
10.2.7.2.2.6
Global Event Counting
10.2.7.2.2.7
Local Event to Global Event Conversion
10.2.7.2.2.8
Global Event Multicast
10.2.8
Packet Streaming Interface Link (PSI-L)
10.2.8.1
PSI-L Overview
10.2.8.2
PSI-L Functional Description
10.2.8.2.1
PSI-L Introduction
10.2.8.2.2
PSI-L Operation
10.2.8.2.2.1
Event Transport
10.2.8.2.2.2
Threads
10.2.8.2.2.3
Arbitration Protocol
10.2.8.2.2.4
Thread Configuration
10.2.8.2.2.4.1
Thread Pairing
10.2.8.2.2.4.1.1
Configuration Transaction Pairing
10.2.8.2.2.4.2
Configuration Registers Region
10.2.9
NAVSS North Bridge (NB)
10.2.9.1
NB Overview
10.2.9.1.1
Features Supported
10.2.9.1.2
NB Parameters
10.2.9.1.2.1
Compliance to Standards
10.2.9.1.2.2
Features Not Supported
10.2.9.2
NB Functional Description
10.2.9.2.1
VBUSM Slave Interfaces
10.2.9.2.2
VBUSM Master Interface
10.2.9.2.3
VBUSM.C Interfaces
10.2.9.2.3.1
Multi-Threading
10.2.9.2.3.2
Write Command Crediting
10.2.9.2.3.3
Early Credit Response
10.2.9.2.3.4
Priority Escalation
10.2.9.2.4
Source M2M Bridges
10.2.9.2.5
Destination M2M Bridge
10.2.9.2.6
M2C Bridge
10.2.9.2.7
Memory Attribute Tables
10.2.9.2.8
Outstanding Read Data Limiter
10.2.9.2.9
Ordering
10.2.9.2.10
Quality of Service
10.2.9.2.11
IDLE Behavior
10.2.9.2.12
Clock Power Management
10.3
Peripheral DMA (PDMA)
10.3.1
PDMA Controller
10.3.1.1
PDMA Overview
10.3.1.1.1
PDMA Features
10.3.1.1.1.1
MCU_PDMA0 (MCU_PDMA_MISC_G0) Features
10.3.1.1.1.2
MCU_PDMA1 (MCU_PDMA_MISC_G1) Features
10.3.1.1.1.3
MCU_PDMA2 (MCU_PDMA_MISC_G2) Features
10.3.1.1.1.4
MCU_PDMA3 (MCU_PDMA_ADC) Features
10.3.1.1.1.5
PDMA5 (PDMA_MCAN) Features
10.3.1.1.1.6
PDMA6 (PDMA_MCASP_G0) Features
10.3.1.1.1.7
PDMA9 (PDMA_SPI_G0) Features
10.3.1.1.1.8
PDMA10 (PDMA_SPI_G1) Features
10.3.1.1.1.9
PDMA13 (PDMA_USART_G0) Features
10.3.1.1.1.10
PDMA14 (PDMA_USART_G1) Features
10.3.1.1.1.11
PDMA15 (PDMA_USART_G2) Features
10.3.1.1.2
Peripheral DMA (PDMA) Ports
10.3.1.2
PDMA Functional Description
10.3.1.2.1
PDMA Functional Blocks
10.3.1.2.1.1
Scheduler
10.3.1.2.1.2
Tx Per-Channel Buffers (TCP FIFO)
10.3.1.2.1.3
Tx DMA Unit (Tx Engine)
10.3.1.2.1.4
Rx Per-Channel Buffers (RCP FIFO)
10.3.1.2.1.5
Rx DMA Unit (Rx Engine)
10.3.1.2.2
PDMA General Functionality
10.3.1.2.2.1
Operational States
10.3.1.2.2.2
Clock Stop
10.3.1.2.2.3
Emulation Control
10.3.1.2.3
PDMA Events and Flow Control
10.3.1.2.3.1
Channel Types
10.3.1.2.3.1.1
X-Y FIFO Mode
10.3.1.2.3.1.2
MCAN Mode
10.3.1.2.3.1.3
AASRC Mode
10.3.1.2.3.2
Channel Triggering
10.3.1.2.3.3
Completion Events
10.3.1.2.4
PDMA Transmit Operation
10.3.1.2.4.1
Destination (Tx) Channel Allocation
10.3.1.2.4.2
Destination (Tx) Channel Out-of-Band Signals
10.3.1.2.4.3
Destination Channel Initialization
10.3.1.2.4.3.1
PSI-L Destination Thread Pairing
10.3.1.2.4.3.2
Static Transfer Request Setup
10.3.1.2.4.3.3
PSI-L Destination Thread Enables
10.3.1.2.4.4
Data Transfer
10.3.1.2.4.4.1
X-Y FIFO Mode Channel
10.3.1.2.4.4.1.1
X-Y FIFO Burst Mode
10.3.1.2.4.4.2
MCAN Mode Channel
10.3.1.2.4.4.2.1
MCAN Burst Mode
10.3.1.2.4.4.3
AASRC Mode Channel
10.3.1.2.4.5
Tx Pause
10.3.1.2.4.6
Tx Teardown
10.3.1.2.4.7
Tx Channel Reset
10.3.1.2.4.8
Tx Debug/State Registers
10.3.1.2.5
PDMA Receive Operation
10.3.1.2.5.1
Source (Rx) Channel Allocation
10.3.1.2.5.2
Source Channel Initialization
10.3.1.2.5.2.1
PSI-L Source Thread Pairing
10.3.1.2.5.2.2
Static Transfer Request Setup
10.3.1.2.5.2.3
PSI-L Source Thread Enables
10.3.1.2.5.3
Data Transfer
10.3.1.2.5.3.1
X-Y FIFO Mode Channel
10.3.1.2.5.3.2
MCAN Mode Channel
10.3.1.2.5.3.2.1
MCAN Burst Mode
10.3.1.2.5.3.3
AASRC Mode Channel
10.3.1.2.5.4
Rx Pause
10.3.1.2.5.5
Rx Teardown
10.3.1.2.5.6
Rx Channel Reset
10.3.1.2.5.7
Rx Debug/State Register
10.3.1.2.6
PDMA ECC Support
10.3.1.3
PDMA Registers
10.3.1.3.1
PDMA PSI-L TX Configuration Registers
10.3.1.3.2
PDMA PSI-L RX Configuration Registers
10.3.2
PDMA Sources
10.3.2.1
MCU Domain PDMA Event Maps
10.3.2.1.1
MCU_PDMA_MISC_G0 Event Map
10.3.2.1.2
MCU_PDMA_MISC_G1 Event Map
10.3.2.1.3
MCU_PDMA_MISC_G2 Event Map
10.3.2.1.4
MCU_PDMA_ADC Event Map
10.3.2.2
MAIN Domain PDMA Event Maps
10.3.2.2.1
PDMA_MCAN Event Map
10.3.2.2.2
PDMA_MCASP_G0 Event Map
10.3.2.2.3
PDMA_SPI_G0 Event Map
10.3.2.2.4
PDMA_SPI_G1 Event Map
10.3.2.2.5
PDMA_USART_G0 Event Map
10.3.2.2.6
PDMA_USART_G1 Event Map
10.3.2.2.7
PDMA_USART_G2 Event Map
10.4
Data Routing Unit (DRU)
10.4.1
DRU Overview
10.4.1.1
Data Routing Unit (DRU) Ports
10.4.2
DRU Integration
10.4.3
DRU Functional Description
10.4.3.1
DRU Basic Functionality
10.4.3.1.1
Queues
10.4.3.1.2
Channel Configuration
10.4.3.1.2.1
Non-realtime Channel Configuration
10.4.3.1.2.2
Realtime Channel Configuration
10.4.3.1.3
TR Submission
10.4.3.1.3.1
Direct TR Submission
10.4.3.1.3.2
PSI-L TR Submission
10.4.3.1.4
TR Removal from Channel
10.4.3.1.5
Channel Tear Down
10.4.3.1.5.1
Tear Down Completion
10.4.3.2
DRU Virtualization
10.4.3.3
DRU Compression and Decompression
10.4.3.4
DRU Output Events
10.4.3.5
DRU Address Fetch Algorithm, TR and CR Formats
10.4.3.5.1
Transpose
10.4.3.5.2
Circular Buffering
10.4.3.6
DRU Firewalls
10.4.3.7
DRU Errors
10.4.3.8
DRU Configurations
11
Time Sync
11.1
Time Sync Module (CPTS)
11.1.1
CPTS Overview
11.1.1.1
CPTS Features
11.1.2
CPTS Functional Description
11.1.2.1
CPTS Architecture
11.1.2.2
CPTS Initialization
11.1.2.3
32-bit Time Stamp Value
11.1.2.4
64-bit Time Stamp Value
11.1.2.4.1
64-Bit Timestamp Nudge
11.1.2.4.2
64-bit Timestamp PPM
11.1.2.5
Event FIFO
11.1.2.6
Timestamp Compare Output
11.1.2.6.1
Non-Toggle Mode
11.1.2.6.2
Toggle Mode
11.1.2.7
Timestamp Sync Output
11.1.2.8
Timestamp GENF Output
11.1.2.8.1
GENFn Nudge
11.1.2.8.2
GENFn PPM
11.1.2.9
Time Sync Events
11.1.2.9.1
Time Stamp Push Event
11.1.2.9.2
Time Stamp Counter Rollover Event (32-bit mode only)
11.1.2.9.3
Time Stamp Counter Half-rollover Event (32-bit mode only)
11.1.2.9.4
Hardware Time Stamp Push Event
11.1.2.10
Timestamp Compare Event
11.1.2.11
CPTS Interrupt Handling
11.2
Timer Manager
11.2.1
Timer Manager Overview
11.2.1.1
Timer Manager Features
11.2.2
Timer Manager Functional Description
11.2.2.1
Timer Manager Function Overview
11.2.2.2
Timer Counter
11.2.2.2.1
Timer Counter Rollover
11.2.2.3
Timer Control Module (FSM)
11.2.2.4
Timer Reprogramming
11.2.2.5
Event FIFO
11.2.2.6
Output Event Lookup (OES RAM)
11.2.3
Timer Manager Programming Guide
11.2.3.1
Timer Manager Low-level Programming Models
11.2.3.1.1
Initialization Sequence
11.2.3.1.2
Real-time Operating Requirements
11.2.3.1.2.1
Timer Touch
11.2.3.1.2.2
Timer Disable
11.2.3.1.2.3
Timer Enable
11.2.3.1.3
Power Up/Power Down Sequence
11.3
Time Sync and Compare Events
11.3.1
Time Sync Architecture
11.3.1.1
Time Sync Architecture Overview
11.3.2
Time Sync Routers
11.3.2.1
Time Sync Routers Overview
11.3.3
Time Sync Event Sources
12
Peripherals
12.1
General Connectivity Peripherals
12.1.1
Analog-to-Digital Converter (ADC)
12.1.1.1
ADC Overview
12.1.1.1.1
ADC Features
12.1.1.1.2
ADC Ports
12.1.1.2
ADC Environment
12.1.1.3
ADC Functional Description
12.1.1.3.1
ADC FSM Sequencer Functional Description
12.1.1.3.1.1
Step Enable
12.1.1.3.1.2
Step Configuration
12.1.1.3.1.2.1
One-Shot (Single) or Continuous Mode
12.1.1.3.1.2.2
Software- or Hardware-Enabled Steps
12.1.1.3.1.2.3
Averaging of Samples
12.1.1.3.1.2.4
Analog Multiplexer Input Select
12.1.1.3.1.2.5
Differential Control
12.1.1.3.1.2.6
FIFO Select
12.1.1.3.1.2.7
Range Check Interrupt Enable
12.1.1.3.1.3
Open Delay and Sample Delay
12.1.1.3.1.3.1
Open Delay
12.1.1.3.1.3.2
Sample Delay
12.1.1.3.1.4
Interrupts
12.1.1.3.1.5
Power Management
12.1.1.3.1.6
DMA Requests
12.1.1.3.2
ADC AFE Functional Description
12.1.1.3.2.1
AFE Functional Block Diagram
12.1.1.3.3
ADC FIFOs and DMA
12.1.1.3.3.1
FIFOs
12.1.1.3.3.2
DMA
12.1.1.3.4
ADC Error Correcting Code (ECC)
12.1.1.3.4.1
Testing ECC Error Injection
12.1.1.3.5
ADC Functional Debug Mode
12.1.1.4
ADC Programming Guide
12.1.1.4.1
ADC Low-Level Programming Models
12.1.1.4.1.1
During Operation
12.1.2
General-Purpose Interface (GPIO)
12.1.2.1
GPIO Overview
12.1.2.1.1
GPIO Features
12.1.2.1.2
GPIO Ports
12.1.2.2
GPIO Environment
12.1.2.3
GPIO Functional Description
12.1.2.3.1
GPIO Block Diagram
12.1.2.3.2
GPIO Function
12.1.2.3.3
GPIO Interrupt and Event Generation
12.1.2.3.3.1
Interrupt Enable (per Bank)
12.1.2.3.3.2
Trigger Configuration (per Bit)
12.1.2.3.3.3
Interrupt Status and Clear (per Bit)
12.1.2.3.4
GPIO Emulation Halt Operation
12.1.2.4
GPIO Programming Guide
12.1.2.4.1
GPIO Low-Level Programming Models
12.1.2.4.1.1
GPIO Operational Modes Configuration
12.1.2.4.1.1.1
GPIO Read Input Register
12.1.2.4.1.1.2
GPIO Set Bit Function
12.1.2.4.1.1.3
GPIO Clear Bit Function
12.1.3
Inter-Integrated Circuit (I2C) Interface
12.1.3.1
I2C Overview
12.1.3.1.1
I2C Features
12.1.3.1.2
I2C Ports
12.1.3.2
I2C Environment
12.1.3.3
I2C Functional Description
12.1.3.3.1
I2C Block Diagram
12.1.3.3.2
I2C Clocks
12.1.3.3.2.1
I2C Clocking
12.1.3.3.2.2
I2C Automatic Blocking of the I2C Clock Feature
12.1.3.3.3
I2C Software Reset
12.1.3.3.4
I2C Power Management
12.1.3.3.5
I2C Interrupt Requests
12.1.3.3.6
I2C Programmable Multitarget Channel Feature
12.1.3.3.7
I2C FIFO Management
12.1.3.3.7.1
I2C FIFO Interrupt Mode
12.1.3.3.7.2
I2C FIFO Polling Mode
12.1.3.3.7.3
I2C Draining Feature
12.1.3.3.8
I2C Noise Filter
12.1.3.3.9
I2C System Test Mode
12.1.3.4
I2C Programming Guide
12.1.3.4.1
I2C Low-Level Programming Models
12.1.3.4.1.1
I2C Programming Model
12.1.3.4.1.1.1
Main Program
12.1.3.4.1.1.1.1
Configure the Module Before Enabling the I2C Controller
12.1.3.4.1.1.1.2
Initialize the I2C Controller
12.1.3.4.1.1.1.3
Configure Target Address and the Data Control Register
12.1.3.4.1.1.1.4
Initiate a Transfer
12.1.3.4.1.1.1.5
Receive Data
12.1.3.4.1.1.1.6
Transmit Data
12.1.3.4.1.1.2
Interrupt Subroutine Sequence
12.1.3.4.1.1.3
Programming Flow-Diagrams
12.1.4
Improved Inter-Integrated Circuit (I3C) Interface
12.1.4.1
I3C Overview
12.1.4.1.1
I3C Features
12.1.4.1.2
I3C Ports
12.1.4.2
I3C Environment
12.1.4.3
I3C Functional Description
12.1.4.3.1
I3C Block Diagram
12.1.4.3.2
I3C Clock Configuration
12.1.4.3.2.1
Setting Base Frequencies
12.1.4.3.2.2
Asymmetric Push-Pull SCL Timing
12.1.4.3.2.3
Open-Drain SCL Timing
12.1.4.3.2.4
Changing Programmed Frequencies
12.1.4.3.3
I3C Interrupt Requests
12.1.4.3.4
I3C Power Configuration
12.1.4.3.5
I3C Dynamic Address Management
12.1.4.3.6
I3C Retaining Registers Space
12.1.4.3.7
I3C Dynamic Address Assignment Procedure
12.1.4.3.8
I3C Sending CCC Messages
12.1.4.3.9
I3C In-Band Interrupt
12.1.4.3.9.1
Regular I3C Slave In-Band Interrupt
12.1.4.3.9.2
Current Master Takeover In-Band Interrupt
12.1.4.3.10
I3C Hot-Join Request
12.1.4.3.11
I3C Immediate Commands
12.1.4.3.12
I3C Host Commands
12.1.4.3.13
I3C Sending Private Data in SDR Messages
12.1.4.3.13.1
SDR Private Write Message
12.1.4.3.13.2
SDR Private Read Message
12.1.4.3.13.3
SDR Payload Length Adjustment
12.1.4.4
I3C Programming Guide
12.1.4.4.1
I3C Power-On Programming Model
12.1.4.4.2
I3C Static Devices Programming
12.1.4.4.3
I3C DAA Procedure Initiation
12.1.4.4.4
I3C SDR Write Message Programming Model
12.1.4.4.5
I3C SDR Read Message Programming Model
12.1.4.4.6
I3C DDR Write Message Programming Model
12.1.4.4.7
I3C DDR Read Message Programming Model
12.1.5
Multichannel Serial Peripheral Interface (MCSPI)
12.1.5.1
MCSPI Overview
12.1.5.1.1
SPI Features
12.1.5.1.2
MCSPI Ports
12.1.5.2
MCSPI Environment
12.1.5.3
MCSPI Functional Description
12.1.5.3.1
SPI Block Diagram
12.1.5.3.2
MCSPI Reset
12.1.5.3.3
MCSPI Controller Mode
12.1.5.3.3.1
Controller Mode Features
12.1.5.3.3.2
Controller Transmit-and-Receive Mode (Full Duplex)
12.1.5.3.3.3
Controller Transmit-Only Mode (Half Duplex)
12.1.5.3.3.4
Controller Receive-Only Mode (Half Duplex)
12.1.5.3.3.5
Single-Channel Controller Mode
12.1.5.3.3.5.1
Programming Tips When Switching to Another Channel
12.1.5.3.3.5.2
Force SPIEN[i] Mode
12.1.5.3.3.5.3
Turbo Mode
12.1.5.3.3.6
Start-Bit Mode
12.1.5.3.3.7
Chip-Select Timing Control
12.1.5.3.3.8
Programmable MCSPI Clock (SPICLK)
12.1.5.3.3.8.1
Clock Ratio Granularity
12.1.5.3.4
MCSPI Peripheral Mode
12.1.5.3.4.1
Dedicated Resources
12.1.5.3.4.2
Peripheral Transmit-and-Receive Mode
12.1.5.3.4.3
Peripheral Transmit-Only Mode
12.1.5.3.4.4
Peripheral Receive-Only Mode
12.1.5.3.5
MCSPI 3-Pin or 4-Pin Mode
12.1.5.3.6
MCSPI FIFO Buffer Management
12.1.5.3.6.1
Buffer Almost Full
12.1.5.3.6.2
Buffer Almost Empty
12.1.5.3.6.3
End of Transfer Management
12.1.5.3.6.4
Multiple MCSPI Word Access
12.1.5.3.6.5
First MCSPI Word Delay
12.1.5.3.7
MCSPI Interrupts
12.1.5.3.7.1
Interrupt Events in Controller Mode
12.1.5.3.7.1.1
TXx_EMPTY
12.1.5.3.7.1.2
TXx_UNDERFLOW
12.1.5.3.7.1.3
RXx_ FULL
12.1.5.3.7.1.4
End Of Word Count
12.1.5.3.7.2
Interrupt Events in Peripheral Mode
12.1.5.3.7.2.1
TXx_EMPTY
12.1.5.3.7.2.2
TXx_UNDERFLOW
12.1.5.3.7.2.3
RXx_FULL
12.1.5.3.7.2.4
RX0_OVERFLOW
12.1.5.3.7.2.5
End Of Word Count
12.1.5.3.7.3
Interrupt-Driven Operation
12.1.5.3.7.4
Polling
12.1.5.3.8
MCSPI DMA Requests
12.1.5.3.9
MCSPI Power Saving Management
12.1.5.3.9.1
Normal Mode
12.1.5.3.9.2
Idle Mode
12.1.5.3.9.2.1
Force-Idle Mode
12.1.5.4
MCSPI Programming Guide
12.1.5.4.1
MCSPI Operational Mode Configuration
12.1.5.4.1.1
MCSPI Operational Modes
12.1.5.4.1.1.1
Common Transfer Sequence
12.1.5.4.1.1.2
End of Transfer Sequences
12.1.5.4.1.1.3
Transmit-and-Receive (Controller and Peripheral)
12.1.5.4.1.1.4
Transmit-Only (Controller and Peripheral)
12.1.5.4.1.1.4.1
Based on Interrupt Requests
12.1.5.4.1.1.4.2
Based on DMA Write Requests
12.1.5.4.1.1.5
Controller Normal Receive-Only
12.1.5.4.1.1.5.1
Based on Interrupt Requests
12.1.5.4.1.1.5.2
Based on DMA Read Requests
12.1.5.4.1.1.6
Controller Turbo Receive-Only
12.1.5.4.1.1.6.1
Based on Interrupt Requests
12.1.5.4.1.1.6.2
Based on DMA Read Requests
12.1.5.4.1.1.7
Peripheral Receive-Only
12.1.5.4.1.1.8
Transfer Procedures With FIFO
12.1.5.4.1.1.8.1
Common Transfer Sequence in FIFO Mode
12.1.5.4.1.1.8.2
End of Transfer Sequences in FIFO Mode
12.1.5.4.1.1.8.3
Transmit-and-Receive With Word Count
12.1.5.4.1.1.8.4
Transmit-and-Receive Without Word Count
12.1.5.4.1.1.8.5
Transmit-Only
12.1.5.4.1.1.8.6
Receive-Only With Word Count
12.1.5.4.1.1.8.7
Receive-Only Without Word Count
12.1.5.4.1.1.9
Common Transfer Procedures Without FIFO – Polling Method
12.1.5.4.1.1.9.1
Receive-Only Procedure – Polling Method
12.1.5.4.1.1.9.2
Receive-Only Procedure – Interrupt Method
12.1.5.4.1.1.9.3
Transmit-Only Procedure – Polling Method
12.1.5.4.1.1.9.4
Transmit-and-Receive Procedure – Polling Method
12.1.6
Universal Asynchronous Receiver/Transmitter (UART)
12.1.6.1
UART Overview
12.1.6.1.1
UART Features
12.1.6.1.2
IrDA Features
12.1.6.1.3
CIR Features
12.1.6.1.4
UART Ports
12.1.6.2
UART Environment
12.1.6.3
UART Functional Description
12.1.6.3.1
UART Block Diagram
12.1.6.3.2
UART Clock Configuration
12.1.6.3.3
UART Software Reset
12.1.6.3.3.1
Independent TX/RX
12.1.6.3.4
UART Power Management
12.1.6.3.4.1
UART Mode Power Management
12.1.6.3.4.1.1
Module Power Saving
12.1.6.3.4.1.2
System Power Saving
12.1.6.3.4.2
IrDA Mode Power Management
12.1.6.3.4.2.1
Module Power Saving
12.1.6.3.4.2.2
System Power Saving
12.1.6.3.4.3
CIR Mode Power Management
12.1.6.3.4.3.1
Module Power Saving
12.1.6.3.4.3.2
System Power Saving
12.1.6.3.4.4
Local Power Management
12.1.6.3.5
UART Interrupt Requests
12.1.6.3.5.1
UART Mode Interrupt Management
12.1.6.3.5.1.1
UART Interrupts
12.1.6.3.5.1.2
Wake-Up Interrupt
12.1.6.3.5.2
IrDA Mode Interrupt Management
12.1.6.3.5.2.1
IrDA Interrupts
12.1.6.3.5.2.2
Wake-Up Interrupts
12.1.6.3.5.3
CIR Mode Interrupt Management
12.1.6.3.5.3.1
CIR Interrupts
12.1.6.3.5.3.2
Wake-Up Interrupts
12.1.6.3.6
UART FIFO Management
12.1.6.3.6.1
FIFO Trigger
12.1.6.3.6.1.1
Transmit FIFO Trigger
12.1.6.3.6.1.2
Receive FIFO Trigger
12.1.6.3.6.2
FIFO Interrupt Mode
12.1.6.3.6.3
FIFO Polled Mode Operation
12.1.6.3.6.4
FIFO DMA Mode Operation
12.1.6.3.6.4.1
DMA sequence to disable TX DMA
12.1.6.3.6.4.2
DMA Transfers (DMA Mode 1, 2, or 3)
12.1.6.3.6.4.3
DMA Transmission
12.1.6.3.6.4.4
DMA Reception
12.1.6.3.7
UART Mode Selection
12.1.6.3.7.1
Register Access Modes
12.1.6.3.7.1.1
Operational Mode and Configuration Modes
12.1.6.3.7.1.2
Register Access Submode
12.1.6.3.7.1.3
Registers Available for the Register Access Modes
12.1.6.3.7.2
UART/RS-485/IrDA (SIR, MIR, FIR)/CIR Mode Selection
12.1.6.3.7.2.1
Registers Available for the UART Function
12.1.6.3.7.2.2
Registers Available for the IrDA Function
12.1.6.3.7.2.3
Registers Available for the CIR Function
12.1.6.3.8
UART Protocol Formatting
12.1.6.3.8.1
UART Mode
12.1.6.3.8.1.1
UART Clock Generation: Baud Rate Generation
12.1.6.3.8.1.2
Choosing the Appropriate Divisor Value
12.1.6.3.8.1.3
UART Data Formatting
12.1.6.3.8.1.3.1
Frame Formatting
12.1.6.3.8.1.3.2
Hardware Flow Control
12.1.6.3.8.1.3.3
Software Flow Control
1.6.3.8.1.3.3.1
Receive (RX)
1.6.3.8.1.3.3.2
Transmit (TX)
12.1.6.3.8.1.3.4
Autobauding Modes
12.1.6.3.8.1.3.5
Error Detection
12.1.6.3.8.1.3.6
Overrun During Receive
12.1.6.3.8.1.3.7
Time-Out and Break Conditions
1.6.3.8.1.3.7.1
Time-Out Counter
1.6.3.8.1.3.7.2
Break Condition
12.1.6.3.8.2
RS-485 Mode
12.1.6.3.8.2.1
RS-485 External Transceiver Direction Control
12.1.6.3.8.3
IrDA Mode
12.1.6.3.8.3.1
IrDA Clock Generation: Baud Generator
12.1.6.3.8.3.2
Choosing the Appropriate Divisor Value
12.1.6.3.8.3.3
IrDA Data Formatting
12.1.6.3.8.3.3.1
IR RX Polarity Control
12.1.6.3.8.3.3.2
IrDA Reception Control
12.1.6.3.8.3.3.3
IR Address Checking
12.1.6.3.8.3.3.4
Frame Closing
12.1.6.3.8.3.3.5
Store and Controlled Transmission
12.1.6.3.8.3.3.6
Error Detection
12.1.6.3.8.3.3.7
Underrun During Transmission
12.1.6.3.8.3.3.8
Overrun During Receive
12.1.6.3.8.3.3.9
Status FIFO
12.1.6.3.8.3.3.10
Multi-drop Parity Mode with Address Match
12.1.6.3.8.3.3.11
Time-guard
12.1.6.3.8.3.4
SIR Mode Data Formatting
12.1.6.3.8.3.4.1
Abort Sequence
12.1.6.3.8.3.4.2
Pulse Shaping
12.1.6.3.8.3.4.3
SIR Free Format Programming
12.1.6.3.8.3.5
MIR and FIR Mode Data Formatting
12.1.6.3.8.4
CIR Mode
12.1.6.3.8.4.1
CIR Mode Clock Generation
12.1.6.3.8.4.2
CIR Data Formatting
12.1.6.3.8.4.2.1
IR RX Polarity Control
12.1.6.3.8.4.2.2
CIR Transmission
12.1.6.3.8.4.2.3
CIR Reception
12.1.6.4
UART Programming Guide
12.1.6.4.1
UART Mode selection
12.1.6.4.2
UART Submode selection
12.1.6.4.3
UART Load FIFO trigger and DMA mode settings
12.1.6.4.3.1
DMA mode Settings
12.1.6.4.3.2
FIFO Trigger Settings
12.1.6.4.4
UART Protocol, Baud rate and interrupt settings
12.1.6.4.4.1
Baud rate settings
12.1.6.4.4.2
Interrupt settings
12.1.6.4.4.3
Protocol settings
12.1.6.4.4.4
UART/RS-485/IrDA(SIR/MIR/FIR)/CIR
12.1.6.4.4.5
UART Multi-drop Parity Address Match Mode Configuration
12.1.6.4.5
UART Hardware and Software Flow Control Configuration
12.1.6.4.5.1
Hardware Flow Control Configuration
12.1.6.4.5.2
Software Flow Control Configuration
12.1.6.4.6
IrDA Programming Model
12.1.6.4.6.1
SIR mode
12.1.6.4.6.1.1
Receive
12.1.6.4.6.1.2
Transmit
12.1.6.4.6.2
MIR mode
12.1.6.4.6.2.1
Receive
12.1.6.4.6.2.2
Transmit
12.1.6.4.6.3
FIR mode
12.1.6.4.6.3.1
Receive
12.1.6.4.6.3.2
Transmit
12.2
High-speed Serial Interfaces
12.2.1
Gigabit Ethernet MAC (CPSW)
12.2.1.1
CPSW Programming Guide
12.2.1.1.1
Initialization and Configuration of CPSW Subsystem
12.2.1.1.2
CPSW Reset
12.2.1.1.3
MDIO Software Interface
12.2.1.1.3.1
Initializing the MDIO Module
12.2.1.1.3.2
Writing Data To a PHY Register
12.2.1.1.3.3
Reading Data From a PHY Register
12.2.2
Peripheral Component Interconnect Express (PCIe) Subsystem
12.2.2.1
PCIe Subsystem Overview
12.2.2.1.1
PCIe Subsystem Features
12.2.2.1.2
PCIe Subsystem Ports
12.2.2.2
PCIe Environment
12.2.2.3
PCIe Subsystem Functional Description
12.2.2.3.1
PCIe Subsystem Block Diagram
12.2.2.3.1.1
PCIe Core Module
12.2.2.3.1.2
PCIe PHY Interface
12.2.2.3.1.3
CBA Infrastructure
12.2.2.3.1.4
VBUSM to AXI Bridges
12.2.2.3.1.5
AXI to VBUSM Bridges
12.2.2.3.1.6
VBUSP to APB Bridge
12.2.2.3.1.7
Custom Logic
12.2.2.3.2
PCIe Subsystem Reset Schemes
12.2.2.3.2.1
PCIe Conventional Reset
12.2.2.3.2.2
PCIe Function Level Reset
12.2.2.3.2.3
PCIe Reset Isolation
12.2.2.3.2.3.1
Root Port Reset with Device Not Reset
12.2.2.3.2.3.2
Device Reset with Root Port Not Reset
12.2.2.3.2.3.3
End Point Device Reset with Root Port Not Reset
12.2.2.3.2.3.4
Device Reset with End Point Device Not Reset
12.2.2.3.2.4
PCIe Reset Limitations
12.2.2.3.2.5
PCIe Reset Requirements
12.2.2.3.3
PCIe Subsystem Power Management
12.2.2.3.3.1
CBA Power Management
12.2.2.3.4
PCIe Subsystem Interrupts
12.2.2.3.4.1
Interrupts Aggregation
12.2.2.3.4.2
Interrupt Generation in EP Mode
12.2.2.3.4.2.1
Legacy Interrupt Generation in EP Mode
12.2.2.3.4.2.2
MSI and MSI-X Interrupt Generation
12.2.2.3.4.3
Interrupt Reception in EP Mode
12.2.2.3.4.3.1
PCIe Core Downstream Interrupts
12.2.2.3.4.3.2
PCIe Core Function Level Reset Interrupts
12.2.2.3.4.3.3
PCIe Core Power Management Event Interrupts
12.2.2.3.4.3.4
PCIe Core Hot Reset Request Interrupt
12.2.2.3.4.3.5
PTM Valid Interrupt
12.2.2.3.4.4
Interrupt Generation in RP Mode
12.2.2.3.4.5
Interrupt Reception in RP Mode
12.2.2.3.4.5.1
PCIe Legacy Interrupt Reception in RP Mode
12.2.2.3.4.5.2
MSI/MSI-X Interrupt Reception in RP Mode
12.2.2.3.4.5.3
Advanced Error Reporting Interrupt
12.2.2.3.4.6
Common Interrupt Reception in RP and EP Modes
12.2.2.3.4.6.1
PCIe Local Interrupt
12.2.2.3.4.6.2
PHY Interrupt
12.2.2.3.4.6.3
Link down Interrupt
12.2.2.3.4.6.4
Transaction Error Interrupts
12.2.2.3.4.6.5
Power Management Event Interrupt
12.2.2.3.4.6.6
Active Internal Diagnostics Interrupts
12.2.2.3.4.7
ECC Aggregator Interrupts
12.2.2.3.4.8
CPTS Interrupt
12.2.2.3.5
PCIe Subsystem DMA Support
12.2.2.3.5.1
PCIe DMA Support in RP Mode
12.2.2.3.5.2
PCIe DMA Support in EP Mode
12.2.2.3.6
PCIe Subsystem Transactions
12.2.2.3.6.1
PCIe Supported Transactions
12.2.2.3.6.2
PCIe Transaction Limitations
12.2.2.3.7
PCIe Subsystem Address Translation
12.2.2.3.7.1
PCIe Inbound Address Translation
12.2.2.3.7.1.1
Root Port Inbound PCIe to AXI Address Translation
12.2.2.3.7.1.2
End Point Inbound PCIe to AXI Address Translation
12.2.2.3.7.2
PCIe Outbound Address Translation
12.2.2.3.7.2.1
PCIe Outbound Address Translation Bypass
12.2.2.3.8
PCIe Subsystem Virtualization Support
12.2.2.3.8.1
End Point SR-IOV Support
12.2.2.3.8.2
Root Port ATS Support
12.2.2.3.8.3
VirtID Mapping
12.2.2.3.9
PCIe Subsystem Quality-of-Service (QoS)
12.2.2.3.10
PCIe Subsystem Precision Time Measurement (PTM)
12.2.2.3.11
PCIe Subsystem Loopback
12.2.2.3.11.1
PCIe PIPE Loopback
12.2.2.3.11.1.1
PIPE Loopback Master Mode
12.2.2.3.11.1.2
PIPE Loopback Slave Mode
12.2.2.3.12
PCIe Subsystem Error Handling
12.2.2.3.12.1
PCIe AXI to/from VBUSM Bus Error Mapping
12.2.2.3.13
PCIe Subsystem Internal Diagnostics Features
12.2.2.3.13.1
PCIe Parity
12.2.2.3.13.2
ECC Aggregators
12.2.2.3.13.3
RAM ECC Inversion
12.2.2.3.14
LTSSM State Encoding
12.2.3
Universal Serial Bus (USB) Subsystem
12.2.3.1
USB Overview
12.2.3.1.1
USB Features
12.2.3.1.2
USB Ports
12.2.3.1.3
USB Terminology
12.2.3.2
USB Environment
12.2.3.3
USB Functional Description
12.2.3.3.1
USB Type-C Connector Support
12.2.3.3.2
USB Controller Reset
12.2.3.3.3
Overcurrent Detection
12.2.3.3.4
Top-Level Initialization Sequence
12.2.4
Serializer/Deserializer (SerDes)
12.2.4.1
SerDes Overview
12.2.4.1.1
SerDes Features
12.2.4.1.2
SerDes Ports
12.2.4.1.3
Industry Standards Compatibility
12.2.4.2
SerDes Environment
12.2.4.2.1
SerDes I/Os
12.2.4.3
SerDes Integration
12.2.4.3.1
WIZ Settings
12.2.4.3.1.1
Interface Selection
12.2.4.3.1.2
ACSPCIe Reference Clock Selection
12.2.4.4
SerDes Functional Description
12.2.4.4.1
SerDes Block Diagram
12.3
Memory Interfaces
12.3.1
Flash Subsystem (FSS)
12.3.1.1
FSS Overview
12.3.1.1.1
FSS Features
12.3.1.1.2
Flash Ports
12.3.1.2
FSS Environment
12.3.1.3
FSS Functional Description
12.3.1.3.1
FSS Block Diagram
12.3.1.3.2
FSS ECC Support
12.3.1.3.3
FSS Modes of Operation
12.3.1.3.4
FSS Memory Regions
12.3.1.4
FSS Programming Guide
12.3.1.4.1
FSS Initialization Sequence
12.3.1.4.2
FSS Real-Time Operation
12.3.1.4.3
FSS Power Up/Down Sequence
12.3.2
Octal Serial Peripheral Interface (OSPI)
12.3.2.1
OSPI Overview
12.3.2.1.1
OSPI Features
12.3.2.1.2
OSPI Ports
12.3.2.2
OSPI Environment
12.3.2.3
OSPI Functional Description
12.3.2.3.1
OSPI Block Diagram
12.3.2.3.1.1
Data Slave Interface
12.3.2.3.1.2
Configuration Slave Interface
12.3.2.3.1.3
OSPI Clock Domains
12.3.2.3.2
OSPI Modes
12.3.2.3.2.1
Read Data Capture
12.3.2.3.2.1.1
Mechanisms of Data Capturing
12.3.2.3.2.1.2
Data Capturing Mechanism Using Taps
12.3.2.3.2.1.3
Data Capturing Mechanism Using PHY Module
12.3.2.3.2.2
External Pull Down on DQS
12.3.2.3.3
OSPI Power Management
12.3.2.3.4
Auto HW Polling
12.3.2.3.5
Flash Reset
12.3.2.3.6
OSPI Memory Regions
12.3.2.3.7
OSPI Interrupt Requests
12.3.2.3.8
OSPI Data Interface
12.3.2.3.8.1
Data Interface Address Remapping
12.3.2.3.8.2
Write Protection
12.3.2.3.8.3
Access Forwarding
12.3.2.3.9
OSPI Direct Access Controller (DAC)
12.3.2.3.10
OSPI Indirect Access Controller (INDAC)
12.3.2.3.10.1
Indirect Read Controller
12.3.2.3.10.1.1
Indirect Read Transfer Process
12.3.2.3.10.2
Indirect Write Controller
12.3.2.3.10.2.1
Indirect Write Transfer Process
12.3.2.3.10.3
Indirect Access Queuing
12.3.2.3.10.4
Consecutive Writes and Reads Using Indirect Transfers
12.3.2.3.10.5
Accessing the SRAM
12.3.2.3.11
OSPI Software-Triggered Instruction Generator (STIG)
12.3.2.3.11.1
Servicing a STIG Request
12.3.2.3.11.2
2153
12.3.2.3.12
OSPI Arbitration Between Direct / Indirect Access Controller and STIG
12.3.2.3.13
OSPI Command Translation
12.3.2.3.14
Selecting the Flash Instruction Type
12.3.2.3.15
OSPI Data Integrity
12.3.2.3.16
OSPI PHY Module
12.3.2.3.16.1
PHY Pipeline Mode
12.3.2.3.16.2
Read Data Capturing by the PHY Module
12.3.2.4
OSPI Programming Guide
12.3.2.4.1
Configuring the OSPI Controller for Use After Reset
12.3.2.4.2
Configuring the OSPI Controller for Optimal Use
12.3.2.4.3
Using the Flash Command Control Register (STIG Operation)
12.3.2.4.4
Using SPI Legacy Mode
12.3.2.4.5
Entering XIP Mode from POR
12.3.2.4.6
Entering XIP Mode Otherwise
12.3.2.4.7
Exiting XIP Mode
12.3.3
HyperBus Interface
12.3.3.1
HyperBus Overview
12.3.3.1.1
HyperBus Features
12.3.3.1.2
Hyperbus Ports
12.3.3.2
HyperBus Environment
12.3.3.3
HyperBus Functional Description
12.3.3.3.1
HyperBus Interrupts
12.3.3.3.2
HyperBus ECC Support
12.3.3.3.2.1
ECC Aggregator
12.3.3.3.3
HyperBus Internal FIFOs
12.3.3.3.4
HyperBus Data Regions
12.3.3.3.5
HyperBus True Continuous Read (TCR) Mode
12.3.3.4
HyperBus Programming Guide
12.3.3.4.1
HyperBus Initialization Sequence
12.3.3.4.1.1
HyperFlash Access
12.3.3.4.1.2
HyperRAM Access
12.3.3.4.2
HyperBus Real-time Operating Requirements
12.3.3.4.3
HyperBus Power Up/Down Sequence
12.3.4
General-Purpose Memory Controller (GPMC)
12.3.4.1
GPMC Overview
12.3.4.1.1
GPMC Features
12.3.4.1.2
GPMC Ports
12.3.4.2
GPMC Environment
12.3.4.3
GPMC Functional Description
12.3.4.3.1
GPMC Block Diagram
12.3.4.3.2
GPMC Clock Configuration
12.3.4.3.3
GPMC Power Management
12.3.4.3.4
GPMC Interrupt Requests
12.3.4.3.5
GPMC Interconnect Port Interface
12.3.4.3.6
GPMC Address and Data Bus
12.3.4.3.6.1
GPMC I/O Configuration Setting
12.3.4.3.7
GPMC Address Decoder and Chip-Select Configuration
12.3.4.3.7.1
Chip-Select Base Address and Region Size
12.3.4.3.7.2
Access Protocol
12.3.4.3.7.2.1
Supported Devices
12.3.4.3.7.2.2
Access Size Adaptation and Device Width
12.3.4.3.7.2.3
Address/Data-Multiplexing Interface
12.3.4.3.7.3
External Signals
12.3.4.3.7.3.1
WAIT Pin Monitoring Control
12.3.4.3.7.3.1.1
Wait Monitoring During Asynchronous Read Access
12.3.4.3.7.3.1.2
Wait Monitoring During Asynchronous Write Access
12.3.4.3.7.3.1.3
Wait Monitoring During Synchronous Read Access
12.3.4.3.7.3.1.4
Wait Monitoring During Synchronous Write Access
12.3.4.3.7.3.1.5
Wait With NAND Device
12.3.4.3.7.3.1.6
Idle Cycle Control Between Successive Accesses
3.4.3.7.3.1.6.1
Bus Turnaround (BUSTURNAROUND)
3.4.3.7.3.1.6.2
Idle Cycles Between Accesses to Same Chip-Select (CYCLE2CYCLESAMECSEN, CYCLE2CYCLEDELAY)
3.4.3.7.3.1.6.3
Idle Cycles Between Accesses to Different Chip-Select (CYCLE2CYCLEDIFFCSEN, CYCLE2CYCLEDELAY)
12.3.4.3.7.3.1.7
Slow Device Support (TIMEPARAGRANULARITY Parameter)
12.3.4.3.7.3.2
DIR Pin
12.3.4.3.7.3.3
Reset
12.3.4.3.7.3.4
Write Protect Signal (nWP)
12.3.4.3.7.3.5
Byte Enable (nBE1/nBE0)
12.3.4.3.7.4
Error Handling
12.3.4.3.8
GPMC Timing Setting
12.3.4.3.8.1
Read Cycle Time and Write Cycle Time (RDCYCLETIME / WRCYCLETIME)
12.3.4.3.8.2
nCS: Chip-Select Signal Control Assertion/Deassertion Time (CSONTIME / CSRDOFFTIME / CSWROFFTIME / CSEXTRADELAY)
12.3.4.3.8.3
nADV/ALE: Address Valid/Address Latch Enable Signal Control Assertion/Deassertion Time (ADVONTIME / ADVRDOFFTIME / ADVWROFFTIME / ADVEXTRADELAY/ADVAADMUXONTIME/ADVAADMUXRDOFFTIME/ADVAADMUXWROFFTIME)
12.3.4.3.8.4
nOE/nRE: Output Enable/Read Enable Signal Control Assertion/Deassertion Time (OEONTIME / OEOFFTIME / OEEXTRADELAY / OEAADMUXONTIME / OEAADMUXOFFTIME)
12.3.4.3.8.5
nWE: Write Enable Signal Control Assertion/Deassertion Time (WEONTIME / WEOFFTIME / WEEXTRADELAY)
12.3.4.3.8.6
GPMC_CLKOUT
12.3.4.3.8.7
GPMC Output Clock and Control Signals Setup and Hold
12.3.4.3.8.8
Access Time (RDACCESSTIME / WRACCESSTIME)
12.3.4.3.8.8.1
Access Time on Read Access
12.3.4.3.8.8.2
Access Time on Write Access
12.3.4.3.8.9
Page Burst Access Time (PAGEBURSTACCESSTIME)
12.3.4.3.8.9.1
Page Burst Access Time on Read Access
12.3.4.3.8.9.2
Page Burst Access Time on Write Access
12.3.4.3.8.10
Bus Keeping Support
12.3.4.3.9
GPMC NOR Access Description
12.3.4.3.9.1
Asynchronous Access Description
12.3.4.3.9.1.1
Access on Address/Data Multiplexed Devices
12.3.4.3.9.1.1.1
Asynchronous Single-Read Operation on an Address/Data Multiplexed Device
12.3.4.3.9.1.1.2
Asynchronous Single-Write Operation on an Address/Data-Multiplexed Device
12.3.4.3.9.1.1.3
Asynchronous Multiple (Page) Write Operation on an Address/Data-Multiplexed Device
12.3.4.3.9.1.2
Access on Address/Address/Data-Multiplexed Devices
12.3.4.3.9.1.2.1
Asynchronous Single Read Operation on an AAD-Multiplexed Device
12.3.4.3.9.1.2.2
Asynchronous Single-Write Operation on an AAD-Multiplexed Device
12.3.4.3.9.1.2.3
Asynchronous Multiple (Page) Read Operation on an AAD-Multiplexed Device
12.3.4.3.9.2
Synchronous Access Description
12.3.4.3.9.2.1
Synchronous Single Read
12.3.4.3.9.2.2
Synchronous Multiple (Burst) Read (4-, 8-, 16-Word16 Burst With Wraparound Capability)
12.3.4.3.9.2.3
Synchronous Single Write
12.3.4.3.9.2.4
Synchronous Multiple (Burst) Write
12.3.4.3.9.3
Asynchronous and Synchronous Accesses in non-multiplexed Mode
12.3.4.3.9.3.1
Asynchronous Single-Read Operation on non-multiplexed Device
12.3.4.3.9.3.2
Asynchronous Single-Write Operation on non-multiplexed Device
12.3.4.3.9.3.3
Asynchronous Multiple (Page Mode) Read Operation on non-multiplexed Device
12.3.4.3.9.3.4
Synchronous Operations on a non-multiplexed Device
12.3.4.3.9.4
Page and Burst Support
12.3.4.3.9.5
System Burst vs External Device Burst Support
12.3.4.3.10
GPMC pSRAM Access Specificities
12.3.4.3.11
GPMC NAND Access Description
12.3.4.3.11.1
NAND Memory Device in Byte or 16-bit Word Stream Mode
12.3.4.3.11.1.1
Chip-Select Configuration for NAND Interfacing in Byte or Word Stream Mode
12.3.4.3.11.1.2
NAND Device Command and Address Phase Control
12.3.4.3.11.1.3
Command Latch Cycle
12.3.4.3.11.1.4
Address Latch Cycle
12.3.4.3.11.1.5
NAND Device Data Read and Write Phase Control in Stream Mode
12.3.4.3.11.1.6
NAND Device General Chip-Select Timing Control Requirement
12.3.4.3.11.1.7
Read and Write Access Size Adaptation
12.3.4.3.11.1.7.1
8-Bit-Wide NAND Device
12.3.4.3.11.1.7.2
16-Bit-Wide NAND Device
12.3.4.3.11.2
NAND Device-Ready Pin
12.3.4.3.11.2.1
Ready Pin Monitored by Software Polling
12.3.4.3.11.2.2
Ready Pin Monitored by Hardware Interrupt
12.3.4.3.11.3
ECC Calculator
12.3.4.3.11.3.1
Hamming Code
12.3.4.3.11.3.1.1
ECC Result Register and ECC Computation Accumulation Size
12.3.4.3.11.3.1.2
ECC Enabling
12.3.4.3.11.3.1.3
ECC Computation
12.3.4.3.11.3.1.4
ECC Comparison and Correction
12.3.4.3.11.3.1.5
ECC Calculation Based on 8-Bit Word
12.3.4.3.11.3.1.6
ECC Calculation Based on 16-Bit Word
12.3.4.3.11.3.2
BCH Code
12.3.4.3.11.3.2.1
Requirements
12.3.4.3.11.3.2.2
Memory Mapping of BCH Codeword
3.4.3.11.3.2.2.1
Memory Mapping of Data Message
3.4.3.11.3.2.2.2
Memory-Mapping of the ECC
3.4.3.11.3.2.2.3
Wrapping Modes
4.3.11.3.2.2.3.1
Manual Mode (0x0)
4.3.11.3.2.2.3.2
Mode 0x1
4.3.11.3.2.2.3.3
Mode 0xA (10)
4.3.11.3.2.2.3.4
Mode 0x2
4.3.11.3.2.2.3.5
Mode 0x3
4.3.11.3.2.2.3.6
Mode 0x7
4.3.11.3.2.2.3.7
Mode 0x8
4.3.11.3.2.2.3.8
Mode 0x4
4.3.11.3.2.2.3.9
Mode 0x9
4.3.11.3.2.2.3.10
Mode 0x5
4.3.11.3.2.2.3.11
Mode 0xB (11)
4.3.11.3.2.2.3.12
Mode 0x6
12.3.4.3.11.3.2.3
Supported NAND Page Mappings and ECC Schemes
3.4.3.11.3.2.3.1
Per-Sector Spare Mappings
3.4.3.11.3.2.3.2
Pooled Spare Mapping
3.4.3.11.3.2.3.3
Per-Sector Spare Mapping, with ECC Separated at the End of the Page
12.3.4.3.11.4
Prefetch and Write-Posting Engine
12.3.4.3.11.4.1
General Facts About the Engine Configuration
12.3.4.3.11.4.2
Prefetch Mode
12.3.4.3.11.4.3
FIFO Control in Prefetch Mode
12.3.4.3.11.4.4
Write-Posting Mode
12.3.4.3.11.4.5
FIFO Control in Write-Posting Mode
12.3.4.3.11.4.6
Optimizing NAND Access Using the Prefetch and Write-Posting Engine
12.3.4.3.11.4.7
Interleaved Accesses Between Prefetch and Write-Posting Engine and Other Chip-Selects
12.3.4.3.12
GPMC Use Cases and Tips
12.3.4.3.12.1
How to Set GPMC Timing Parameters for Typical Accesses
12.3.4.3.12.1.1
External Memory Attached to the GPMC Module
12.3.4.3.12.1.2
Typical GPMC Setup
12.3.4.3.12.1.2.1
GPMC Configuration for Synchronous Burst Read Access
12.3.4.3.12.1.2.2
GPMC Configuration for Asynchronous Read Access
12.3.4.3.12.1.2.3
GPMC Configuration for Asynchronous Single Write Access
12.3.4.3.12.2
How to Choose a Suitable Memory to Use With the GPMC
12.3.4.3.12.2.1
Supported Memories or Devices
12.3.4.3.12.2.1.1
Memory Pin Multiplexing
12.3.4.3.12.2.1.2
NAND Interface Protocol
12.3.4.3.12.2.1.3
NOR Interface Protocol
12.3.4.3.12.2.1.4
Other Technologies
12.3.4.4
GPMC Basic Programming Model
12.3.4.4.1
GPMC High-Level Programming Model Overview
12.3.4.4.2
GPMC Initialization
12.3.4.4.3
GPMC Configuration in NOR Mode
12.3.4.4.4
GPMC Configuration in NAND Mode
12.3.4.4.5
Set Memory Access
12.3.4.4.6
GPMC Timing Parameters
12.3.4.4.6.1
GPMC Timing Parameters Formulas
12.3.4.4.6.1.1
NAND Flash Interface Timing Parameters Formulas
12.3.4.4.6.1.2
Synchronous NOR Flash Timing Parameters Formulas
12.3.4.4.6.1.3
Asynchronous NOR Flash Timing Parameters Formulas
12.3.5
Error Location Module (ELM)
12.3.5.1
ELM Overview
12.3.5.1.1
ELM Features
12.3.5.1.2
ELM Ports
12.3.5.2
ELM Functional Description
12.3.5.2.1
ELM Software Reset
12.3.5.2.2
ELM Power Management
12.3.5.2.3
ELM Interrupt Requests
12.3.5.2.4
ELM Processing Initialization
12.3.5.2.5
ELM Processing Sequence
12.3.5.2.6
ELM Processing Completion
12.3.5.3
ELM Basic Programming Model
12.3.5.3.1
ELM Low-Level Programming Model
12.3.5.3.1.1
Processing Initialization
12.3.5.3.1.2
Read Results
12.3.5.3.1.3
2352
12.3.5.3.2
Use Case: ELM Used in Continuous Mode
12.3.5.3.3
Use Case: ELM Used in Page Mode
12.3.6
Multi-Media Card Secure Digital (MMCSD) Interface
12.3.6.1
MMCSD Overview
12.3.6.1.1
MMCSD Features
12.3.6.1.2
MMCSD Ports
12.3.6.2
MMCSD Environment
12.3.6.3
MMCSD Functional Description
12.3.6.3.1
Block Diagram
12.3.6.3.2
Memory Regions
12.3.6.3.3
Interrupt Requests
12.3.6.3.4
ECC Support
12.3.6.3.4.1
ECC Aggregator
12.3.6.3.5
Advanced DMA
12.3.6.3.6
eMMC PHY BIST
12.3.6.3.6.1
BIST Overview
12.3.6.3.6.2
BIST Modes
12.3.6.3.6.2.1
DS Mode
12.3.6.3.6.2.2
HS Mode with TXDLY using DLL
12.3.6.3.6.2.3
HS Mode with TXDLY using Delay Chain
12.3.6.3.6.2.4
DDR50 Mode with TXDLY using DLL
12.3.6.3.6.2.5
DDR50 Mode with TXDLY using Delay Chain
12.3.6.3.6.2.6
HS200 Mode with TX/RXDLY using DLL
12.3.6.3.6.2.7
HS200 Mode with TX/RXDLY using Delay Chain
12.3.6.3.6.2.8
HS400 Mode
12.3.6.3.6.3
BIST Functionality
12.3.6.3.6.4
Signal Interface
12.3.6.3.6.5
Programming Flow
12.3.6.3.6.5.1
DS Mode
12.3.6.3.6.5.1.1
Configuration
12.3.6.3.6.5.1.2
BIST Programming
12.3.6.3.6.5.2
HS Mode with DLY_CHAIN
12.3.6.3.6.5.2.1
Configuration
12.3.6.3.6.5.2.2
BIST Programming
12.3.6.3.6.5.3
HS Mode with DLL
12.3.6.3.6.5.3.1
Configuration
12.3.6.3.6.5.3.2
BIST Programming
12.3.6.3.6.5.4
DDR52 Mode with DLY_CHAIN
12.3.6.3.6.5.4.1
Configuration
12.3.6.3.6.5.4.2
BIST Programming
12.3.6.3.6.5.5
DDR52 Mode with DLL
12.3.6.3.6.5.5.1
Configuration
12.3.6.3.6.5.5.2
BIST Programming
12.3.6.3.6.5.6
HS200 Mode with DLY_CHAIN
12.3.6.3.6.5.6.1
Configuration
12.3.6.3.6.5.6.2
BIST Programming
12.3.6.3.6.5.7
HS200 Mode with DLL
12.3.6.3.6.5.7.1
Configuration
12.3.6.3.6.5.7.2
BIST Programming
12.3.6.3.6.5.8
HS400 Mode with DLL
12.3.6.3.6.5.8.1
Configuration
12.3.6.3.6.5.8.2
BIST Programming
12.3.6.3.6.6
HS200 BIST Result Check Procedure
12.3.6.4
MMCSD Programming Guide
12.3.6.4.1
Sequences
12.3.6.4.1.1
SD Card Detection
12.3.6.4.1.2
SD Clock Control
12.3.6.4.1.2.1
Internal Clock Setup Sequence
12.3.6.4.1.2.2
SD Clock Supply and Stop Sequence
12.3.6.4.1.2.3
SD Clock Frequency Change Sequence
12.3.6.4.1.3
SD Bus Power Control
12.3.6.4.1.4
Changing Bus Width
12.3.6.4.1.5
Timeout Setting on DAT Line
12.3.6.4.1.6
Card Initialization and Identification (for SD I/F)
12.3.6.4.1.6.1
Signal Voltage Switch Procedure (for UHS-I)
12.3.6.4.1.7
SD Transaction Generation
12.3.6.4.1.7.1
Transaction Control without Data Transfer Using DAT Line
12.3.6.4.1.7.1.1
The Sequence to Issue a SD Command
12.3.6.4.1.7.1.2
The Sequence to Finalize a Command
12.3.6.4.1.7.2
Transaction Control with Data Transfer Using DAT Line
12.3.6.4.1.7.2.1
Not using DMA
12.3.6.4.1.7.2.2
Using SDMA
12.3.6.4.1.7.2.3
Using ADMA
12.3.6.4.1.8
Abort Transaction
12.3.6.4.1.8.1
Asynchronous Abort
12.3.6.4.1.8.2
Synchronous Abort
12.3.6.4.1.9
Changing Bus Speed Mode
12.3.6.4.1.10
Error Recovery
12.3.6.4.1.10.1
Error Interrupt Recovery
12.3.6.4.1.10.2
Auto CMD12 Error Recovery
12.3.6.4.1.11
Wakeup Control (Optional)
12.3.6.4.1.12
Suspend/Resume (Optional, Not Supported from Version 4.00)
12.3.6.4.1.12.1
Suspend Sequence
12.3.6.4.1.12.2
Resume Sequence
12.3.6.4.1.12.3
Stop At Block Gap/Continue Timing for Read Transaction
12.3.6.4.1.12.4
Stop At Block Gap/Continue Timing for Write Transaction
12.3.6.4.2
Driver Flow Sequence
12.3.6.4.2.1
Host Controller Setup and Card Detection
12.3.6.4.2.1.1
Host Controller Setup Sequence
12.3.6.4.2.1.2
Card Interface Detection Sequence
12.3.6.4.2.2
Boot Operation
12.3.6.4.2.2.1
Normal Boot Operation: (For Legacy eMMC 5.0)
12.3.6.4.2.2.2
Alternate Boot Operation (For Legacy eMMC 5.0):
12.3.6.4.2.2.3
Boot Code Chunk Read Operation (For Legacy eMMC 5.0):
12.3.6.4.2.3
Retuning procedure (For Legacy Interface)
12.3.6.4.2.3.1
Sampling Clock Tuning
12.3.6.4.2.3.2
Tuning Modes
12.3.6.4.2.3.3
Re-Tuning Mode 2
12.3.6.4.2.4
Command Queuing Driver Flow Sequence
12.3.6.4.2.4.1
Command Queuing Initialization Sequence
12.3.6.4.2.4.2
Task Issuance Sequence
12.3.6.4.2.4.3
Task Execution and Completion Sequence
12.3.6.4.2.4.4
Task Discard and Clear Sequence
12.3.6.4.2.4.5
Error Detect and Recovery when CQ is enabled
12.4
Industrial and Control Interfaces
12.4.1
Enhanced Capture (ECAP) Module
12.4.1.1
ECAP Overview
12.4.1.1.1
ECAP Features
12.4.1.1.2
ECAP Ports
12.4.1.2
ECAP Environment
12.4.1.3
ECAP Functional Description
12.4.1.3.1
Capture and APWM Operating Modes
12.4.1.3.1.1
ECAP Capture Mode Description
12.4.1.3.1.1.1
ECAP Event Prescaler
12.4.1.3.1.1.2
ECAP Edge Polarity Select and Qualifier
12.4.1.3.1.1.3
ECAP Continuous/One-Shot Control
12.4.1.3.1.1.4
ECAP 32-Bit Counter and Phase Control
12.4.1.3.1.1.5
CAP1-CAP4 Registers
12.4.1.3.1.1.6
ECAP Interrupt Control
12.4.1.3.1.1.7
ECAP Shadow Load and Lockout Control
12.4.1.3.1.2
ECAP APWM Mode Operation
12.4.1.3.2
Summary of ECAP Functional Registers
12.4.1.4
ECAP Use Cases
12.4.1.4.1
Absolute Time-Stamp Operation Rising Edge Trigger Example
12.4.1.4.1.1
Code Snippet for CAP Mode Absolute Time, Rising Edge Trigger
12.4.1.4.2
Absolute Time-Stamp Operation Rising and Falling Edge Trigger Example
12.4.1.4.2.1
Code Snippet for CAP Mode Absolute Time, Rising and Falling Edge Trigger
12.4.1.4.3
Time Difference (Delta) Operation Rising Edge Trigger Example
12.4.1.4.3.1
Code Snippet for CAP Mode Delta Time, Rising Edge Trigger
12.4.1.4.4
Time Difference (Delta) Operation Rising and Falling Edge Trigger Example
12.4.1.4.4.1
Code Snippet for CAP Mode Delta Time, Rising and Falling Edge Triggers
12.4.1.4.5
Application of the APWM Mode
12.4.1.4.5.1
Simple PWM Generation (Independent Channel/s) Example
12.4.1.4.5.1.1
Code Snippet for APWM Mode
12.4.1.4.5.2
Multichannel PWM Generation with Synchronization Example
12.4.1.4.5.2.1
Code Snippet for Multichannel PWM Generation with Synchronization
12.4.1.4.5.3
Multichannel PWM Generation with Phase Control Example
12.4.1.4.5.3.1
Code Snippet for Multichannel PWM Generation with Phase Control
12.4.2
Enhanced Pulse Width Modulation (EPWM) Module
12.4.2.1
EPWM Overview
12.4.2.1.1
EPWM Features
12.4.2.1.2
EPWM Ports
12.4.2.2
ECAP Environment
12.4.2.3
EPWM Functional Description
12.4.2.3.1
EPWM Submodule Features
12.4.2.3.1.1
Constant Definitions Used in the EPWM Code Examples
12.4.2.3.2
EPWM Time-Base (TB) Submodule
12.4.2.3.2.1
Overview
12.4.2.3.2.2
Controlling and Monitoring the EPWM Time-Base Submodule
12.4.2.3.2.3
Calculating PWM Period and Frequency
12.4.2.3.2.3.1
EPWM Time-Base Period Shadow Register
12.4.2.3.2.3.2
EPWM Time-Base Counter Synchronization
12.4.2.3.2.4
Phase Locking the Time-Base Clocks of Multiple EPWM Modules
12.4.2.3.2.5
EPWM Time-Base Counter Modes and Timing Waveforms
12.4.2.3.3
EPWM Counter-Compare (CC) Submodule
12.4.2.3.3.1
Overview
12.4.2.3.3.2
Controlling and Monitoring the EPWM Counter-Compare Submodule
12.4.2.3.3.3
Operational Highlights for the EPWM Counter-Compare Submodule
12.4.2.3.3.4
EPWM Counter-Compare Submodule Timing Waveforms
12.4.2.3.4
EPWM Action-Qualifier (AQ) Submodule
12.4.2.3.4.1
Overview
12.4.2.3.4.2
Controlling and Monitoring the EPWM Action-Qualifier Submodule
12.4.2.3.4.3
EPWM Action-Qualifier Event Priority
12.4.2.3.4.4
Waveforms for Common EPWM Configurations
12.4.2.3.5
EPWM Dead-Band Generator (DB) Submodule
12.4.2.3.5.1
Overview
12.4.2.3.5.2
Controlling and Monitoring the EPWM Dead-Band Submodule
12.4.2.3.5.3
Operational Highlights for the EPWM Dead-Band Generator Submodule
12.4.2.3.6
EPWM-Chopper (PC) Submodule
12.4.2.3.6.1
Overview
12.4.2.3.6.2
2523
12.4.2.3.6.3
Controlling the EPWM-Chopper Submodule
12.4.2.3.6.4
Operational Highlights for the EPWM-Chopper Submodule
12.4.2.3.6.5
EPWM-Chopper Waveforms
12.4.2.3.6.5.1
EPWM-Chopper One-Shot Pulse
12.4.2.3.6.5.2
EPWM-Chopper Duty Cycle Control
12.4.2.3.7
EPWM Trip-Zone (TZ) Submodule
12.4.2.3.7.1
Overview
12.4.2.3.7.2
Controlling and Monitoring the EPWM Trip-Zone Submodule
12.4.2.3.7.3
Operational Highlights for the EPWM Trip-Zone Submodule
12.4.2.3.7.4
Generating EPWM Trip-Event Interrupts
12.4.2.3.8
EPWM Event-Trigger (ET) Submodule
12.4.2.3.8.1
Overview
12.4.2.3.8.2
Controlling and Monitoring the EPWM Event-Trigger Submodule
12.4.2.3.8.3
Operational Overview of the EPWM Event-Trigger Submodule
12.4.2.3.8.4
2538
12.4.2.3.9
EPWM High Resolution (HRPWM) Submodule
12.4.2.3.9.1
Overview
12.4.2.3.9.2
Architecture of the High-Resolution PWM Submodule
12.4.2.3.9.3
Controlling and Monitoring the High-Resolution PWM Submodule
12.4.2.3.9.4
Configuring the High-Resolution PWM Submodule
12.4.2.3.9.5
Operational Highlights for the High-Resolution PWM Submodule
12.4.2.3.9.5.1
HRPWM Edge Positioning
12.4.2.3.9.5.2
HRPWM Scaling Considerations
12.4.2.3.9.5.3
HRPWM Duty Cycle Range Limitation
12.4.2.3.10
EPWM / HRPWM Functional Register Groups
12.4.2.3.11
Proper EPWM Interrupt Initialization Procedure
12.4.3
Enhanced Quadrature Encoder Pulse (EQEP) Module
12.4.3.1
EQEP Overview
12.4.3.1.1
EQEP Features
12.4.3.1.2
EQEP Ports
12.4.3.2
EQEP Environment
12.4.3.3
EQEP Functional Description
12.4.3.3.1
EQEP Inputs
12.4.3.3.2
EQEP Quadrature Decoder Unit (QDU)
12.4.3.3.2.1
EQEP Position Counter Input Modes
12.4.3.3.2.1.1
Quadrature Count Mode
12.4.3.3.2.1.2
EQEP Direction-count Mode
12.4.3.3.2.1.3
EQEP Up-Count Mode
12.4.3.3.2.1.4
EQEP Down-Count Mode
12.4.3.3.2.2
EQEP Input Polarity Selection
12.4.3.3.2.3
EQEP Position-Compare Sync Output
12.4.3.3.3
EQEP Position Counter and Control Unit (PCCU)
12.4.3.3.3.1
EQEP Position Counter Operating Modes
12.4.3.3.3.1.1
EQEP Position Counter Reset on Index Event (EQEP_QDEC_QEP_CTL[29-28] PCRM] = 0b00)
12.4.3.3.3.1.2
EQEP Position Counter Reset on Maximum Position (EQEP_QDEC_QEP_CTL[29-28] PCRM=0b01)
12.4.3.3.3.1.3
Position Counter Reset on the First Index Event (EQEP_QDEC_QEP_CTL[29-28] PCRM = 0b10)
12.4.3.3.3.1.4
Position Counter Reset on Unit Time out Event (EQEP_QDEC_QEP_CTL[29-28] PCRM = 0b11)
12.4.3.3.3.2
EQEP Position Counter Latch
12.4.3.3.3.2.1
Index Event Latch
12.4.3.3.3.2.2
EQEP Strobe Event Latch
12.4.3.3.3.3
EQEP Position Counter Initialization
12.4.3.3.3.4
EQEP Position-Compare Unit
12.4.3.3.4
EQEP Edge Capture Unit
12.4.3.3.5
EQEP Watchdog
12.4.3.3.6
Unit Timer Base
12.4.3.3.7
EQEP Interrupt Structure
12.4.3.3.8
Summary of EQEP Functional Registers
12.4.4
Controller Area Network (MCAN)
12.4.4.1
MCAN Overview
12.4.4.1.1
MCAN Features
12.4.4.1.2
MCAN Ports
12.4.4.2
MCAN Environment
12.4.4.3
MCAN Functional Description
12.4.4.3.1
Module Clocking Requirements
12.4.4.3.2
Interrupt and DMA Requests
12.4.4.3.2.1
Interrupt Requests
12.4.4.3.2.2
DMA Requests
12.4.4.3.3
Operating Modes
12.4.4.3.3.1
Software Initialization
12.4.4.3.3.2
Normal Operation
12.4.4.3.3.3
CAN FD Operation
12.4.4.3.3.4
Transmitter Delay Compensation
12.4.4.3.3.4.1
Description
12.4.4.3.3.4.2
Transmitter Delay Compensation Measurement
12.4.4.3.3.5
Restricted Operation Mode
12.4.4.3.3.6
Bus Monitoring Mode
12.4.4.3.3.7
Disabled Automatic Retransmission (DAR) Mode
12.4.4.3.3.7.1
Frame Transmission in DAR Mode
12.4.4.3.3.8
Power Down (Sleep Mode)
12.4.4.3.3.8.1
External Clock Stop Mode
12.4.4.3.3.8.2
Suspend Mode
12.4.4.3.3.8.3
Wakeup request
12.4.4.3.3.9
Test Modes
12.4.4.3.3.9.1
Internal Loopback Mode
12.4.4.3.4
Timestamp Generation
12.4.4.3.4.1
External Timestamp Counter
12.4.4.3.5
Timeout Counter
12.4.4.3.6
ECC Support
12.4.4.3.6.1
ECC Wrapper
12.4.4.3.6.2
ECC Aggregator
12.4.4.3.7
Rx Handling
12.4.4.3.7.1
Acceptance Filtering
12.4.4.3.7.1.1
Range Filter
12.4.4.3.7.1.2
Filter for specific IDs
12.4.4.3.7.1.3
Classic Bit Mask Filter
12.4.4.3.7.1.4
Standard Message ID Filtering
12.4.4.3.7.1.5
Extended Message ID Filtering
12.4.4.3.7.2
Rx FIFOs
12.4.4.3.7.2.1
Rx FIFO Blocking Mode
12.4.4.3.7.2.2
Rx FIFO Overwrite Mode
12.4.4.3.7.3
Dedicated Rx Buffers
12.4.4.3.7.3.1
Rx Buffer Handling
12.4.4.3.7.4
Debug on CAN Support
12.4.4.3.8
Tx Handling
12.4.4.3.8.1
Transmit Pause
12.4.4.3.8.2
Dedicated Tx Buffers
12.4.4.3.8.3
Tx FIFO
12.4.4.3.8.4
Tx Queue
12.4.4.3.8.5
Mixed Dedicated Tx Buffers/Tx FIFO
12.4.4.3.8.6
Mixed Dedicated Tx Buffers/Tx Queue
12.4.4.3.8.7
Transmit Cancellation
12.4.4.3.8.8
Tx Event Handling
12.4.4.3.9
FIFO Acknowledge Handling
12.4.4.3.10
Message RAM
12.4.4.3.10.1
Message RAM Configuration
12.4.4.3.10.2
Rx Buffer and FIFO Element
12.4.4.3.10.3
Tx Buffer Element
12.4.4.3.10.4
Tx Event FIFO Element
12.4.4.3.10.5
Standard Message ID Filter Element
12.4.4.3.10.6
Extended Message ID Filter Element
12.5
Audio Interfaces
12.5.1
Audio Tracking Logic (ATL)
12.5.1.1
ATL Overview
12.5.1.1.1
ATL Features Overview
12.5.1.1.2
ATL Ports
12.5.2
Multichannel Audio Serial Port (MCASP)
12.5.2.1
MCASP Overview
12.5.2.1.1
MCASP Features
12.5.2.1.2
MCASP Ports
12.5.2.2
MCASP Environment
12.5.2.3
MCASP Functional Description
12.5.2.3.1
MCASP Block Diagram
12.5.2.3.2
MCASP Clock and Frame-Sync Configurations
12.5.2.3.2.1
MCASP Transmit Clock
12.5.2.3.2.2
MCASP Receive Clock
12.5.2.3.2.3
Frame-Sync Generator
12.5.2.3.2.4
Synchronous and Asynchronous Transmit and Receive Operations
12.5.2.3.3
MCASP Frame Sync Feedback for Cross Synchronization
12.5.2.3.4
MCASP Serializers
12.5.2.3.5
MCASP Format Units
12.5.2.3.5.1
Transmit Format Unit
12.5.2.3.5.1.1
TDM Mode Transmission Data Alignment Settings
12.5.2.3.5.1.2
DIT Mode Transmission Data Alignment Settings
12.5.2.3.5.2
Receive Format Unit
12.5.2.3.5.2.1
TDM Mode Reception Data Alignment Settings
12.5.2.3.6
MCASP State-Machines
12.5.2.3.7
MCASP TDM Sequencers
12.5.2.3.8
MCASP Software Reset
12.5.2.3.9
MCASP Power Management
12.5.2.3.10
MCASP Transfer Modes
12.5.2.3.10.1
Burst Transfer Mode
12.5.2.3.10.2
Time-Division Multiplexed (TDM) Transfer Mode
12.5.2.3.10.2.1
TDM Time Slots Generation and Processing
12.5.2.3.10.2.2
Special 384-Slot TDM Mode for Connection to External DIR
12.5.2.3.10.3
DIT Transfer Mode
12.5.2.3.10.3.1
Transmit DIT Encoding
12.5.2.3.10.3.2
Transmit DIT Clock and Frame-Sync Generation
12.5.2.3.10.3.3
DIT Channel Status and User Data Register Files
12.5.2.3.11
MCASP Data Transmission and Reception
12.5.2.3.11.1
Data Ready Status and Event/Interrupt Generation
12.5.2.3.11.1.1
Transmit Data Ready
12.5.2.3.11.1.2
Receive Data Ready
12.5.2.3.11.1.3
Transfers Through the Data Port (DATA)
12.5.2.3.11.1.4
Transfers Through the Configuration Bus (CFG)
12.5.2.3.11.1.5
Using a Device CPU for MCASP Servicing
12.5.2.3.11.1.6
Using the DMA for MCASP Servicing
12.5.2.3.12
MCASP Audio FIFO (AFIFO)
12.5.2.3.12.1
AFIFO Data Transmission
12.5.2.3.12.1.1
Transmit DMA Event Pacer
12.5.2.3.12.2
AFIFO Data Reception
12.5.2.3.12.2.1
Receive DMA Event Pacer
12.5.2.3.12.3
Arbitration Between Transmit and Receive DMA Requests
12.5.2.3.13
MCASP Events and Interrupt Requests
12.5.2.3.13.1
Transmit Data Ready Event and Interrupt
12.5.2.3.13.2
Receive Data Ready Event and Interrupt
12.5.2.3.13.3
Error Interrupt
12.5.2.3.13.4
Multiple Interrupts
12.5.2.3.14
MCASP DMA Requests
12.5.2.3.15
MCASP Loopback Modes
12.5.2.3.15.1
Loopback Mode Configurations
12.5.2.3.16
MCASP Error Reporting
12.5.2.3.16.1
Buffer Underrun Error -Transmitter
12.5.2.3.16.2
Buffer Overrun Error-Receiver
12.5.2.3.16.3
DATA Port Error - Transmitter
12.5.2.3.16.4
DATA Port Error - Receiver
12.5.2.3.16.5
Unexpected Frame Sync Error
12.5.2.3.16.6
Clock Failure Detection
12.5.2.3.16.6.1
Clock Failure Check Startup
12.5.2.3.16.6.2
Transmit Clock Failure Check and Recovery
12.5.2.3.16.6.3
Receive Clock Failure Check and Recovery
12.5.2.4
MCASP Programming Guide
12.5.2.4.1
MCASP Operational Modes Configuration
12.5.2.4.1.1
MCASP Transmission Modes
12.5.2.4.1.1.1
Main Sequence – MCASP DIT- /TDM- Polling Transmission Method
12.5.2.4.1.1.2
Main Sequence – MCASP DIT- /TDM - Interrupt Transmission Method
12.5.2.4.1.1.3
Main Sequence –MCASP DIT- /TDM - Mode DMA Transmission Method
12.5.2.4.1.2
MCASP Reception Modes
12.5.2.4.1.2.1
Main Sequence – MCASP Polling Reception Method
12.5.2.4.1.2.2
Main Sequence – MCASP TDM - Interrupt Reception Method
12.5.2.4.1.2.3
Main Sequence – MCASP TDM - Mode DMA Reception Method
12.5.2.4.1.3
MCASP Event Servicing
12.5.2.4.1.3.1
MCASP DIT-/TDM- Transmit Interrupt Events Servicing
12.5.2.4.1.3.2
MCASP TDM- Receive Interrupt Events Servicing
12.5.2.4.1.3.3
Subsequence – MCASP DIT-/TDM -Modes Transmit Error Handling
12.5.2.4.1.3.4
Subsequence – MCASP Receive Error Handling
12.6
Display Subsystem (DSS) and Peripherals
12.6.1
DSS Overview
12.6.1.1
DSS Features
12.6.1.2
DSS Ports
12.6.2
DSS Environment
12.6.2.1
DISPC Environment
12.6.2.1.1
RGB Data Output
12.6.2.1.2
YUV Data Output (BT.656/BT.1120)
12.6.2.1.3
Display Timing Diagrams
12.6.2.1.4
VSYNC/HSYNC/DE Signal Export to SoC Boundary
12.6.2.2
DSI Environment
12.6.2.3
EDP Environment
12.6.3
Display Subsystem Controller (DISPC) with Frame Buffer Decompression Core (FBDC)
12.6.3.1
DISPC Overview
12.6.3.2
DISPC Clocks
12.6.3.3
DISPC Resets
12.6.3.4
DISPC Power Management
12.6.3.5
DISPC Interrupt Requests
12.6.3.6
DISPC DMA Controller
12.6.3.6.1
DISPC DMA Addressing and Bursts
12.6.3.6.2
DISPC Read DMA Buffers
12.6.3.6.3
DISPC Write DMA Buffer
12.6.3.6.4
DISPC Flip/Mirror Support
12.6.3.6.5
DISPC DMA Predecimation
12.6.3.6.6
DISPC DMA Buffer Sharing
12.6.3.6.7
DISPC DMA MFLAG Mechanism
12.6.3.6.8
DISPC DMA Priority Requests Control
12.6.3.6.9
DISPC DMA Arbitration
12.6.3.6.10
DISPC DMA Ultra-Low Power Mode
12.6.3.6.11
DISPC Compressed Data Format Support
12.6.3.6.11.1
FBDC Tile Request
12.6.3.6.11.2
FBDC Source Cropping
12.6.3.7
DISPC Pixel Data Formats
12.6.3.8
DISPC Video Pipeline
12.6.3.8.1
DISPC VID Replication Logic
12.6.3.8.2
DISPC VID VC-1 Range Mapping Unit
12.6.3.8.3
DISPC VID Color Look-Up Table (CLUT)
12.6.3.8.4
DISPC VID Chrominance Resampling
12.6.3.8.4.1
Chrominance Resampling for VID Pipeline
12.6.3.8.4.2
Chrominance Resampling for VIDL Pipeline
12.6.3.8.5
DISPC VID Scaler Unit
12.6.3.8.6
DISPC VID Color Space Conversion YUV to RGB
12.6.3.8.7
DISPC VID Brightness/Contrast/Saturation/Hue Control
12.6.3.8.8
DISPC VID Luma Key Support
12.6.3.8.9
DISPC VID Cropping Support
12.6.3.9
DISPC Write-Back Pipeline
12.6.3.9.1
DISPC WB Color Space Conversion RGB to YUV
12.6.3.9.2
DISPC WB Scaler Unit
12.6.3.10
DISPC Overlay Manager
12.6.3.10.1
DISPC Overlay Input Selector
12.6.3.10.2
DISPC Overlay Mechanism
12.6.3.10.2.1
Overlay Alpha Blender
12.6.3.10.2.2
Overlay Transparency Color Keys
12.6.3.10.3
Overlay 3D Support
12.6.3.10.4
Overlay Color Bar Insertion
12.6.3.11
DISPC Video Port Output
12.6.3.11.1
DISPC VP Gamma Correction Unit
12.6.3.11.2
DISPC VP Color Phase Rotation Unit
12.6.3.11.3
DISPC VP Color Space Conversion - RGB to YUV
12.6.3.11.4
DISPC VP BT.656 and BT.1120 Modes
12.6.3.11.4.1
DISPC BT Mode Blanking
12.6.3.11.4.2
DISPC BT Mode EAV and SAV
12.6.3.11.5
DISPC VP Spatial/Temporal Dithering
12.6.3.11.6
DISPC VP Multiple Cycle Output Format (TDM)
12.6.3.11.7
DISPC VP Stall Mode
12.6.3.11.8
DISPC VP Timing Generator and Display Panel Settings
12.6.3.11.9
DISPC VP Merge-Split-Sync (MSS) Module
12.6.3.11.9.1
MSS Clocking Scheme
12.6.3.11.9.2
MSS Merge with Scaling
12.6.3.12
DISPC Internal Diagnostic Features
12.6.3.12.1
Internal Diagnostic Check Regions
12.6.3.12.2
Internal Diagnostic Signature Generator Using MISR
12.6.3.12.3
Internal Diagnostic Checks
12.6.3.12.4
Internal Diagnostic Check Limitations
12.6.3.13
DISPC Security Management
12.6.3.13.1
Security Implementation
12.6.3.13.2
Secure Mode Configuration
12.6.3.14
DISPC Resources Sharing
12.6.3.14.1
Register Region per Sub-component
12.6.3.14.2
Interrupt Duplication
12.6.3.14.3
Independent Context Update for Pipelines
12.6.3.14.4
CHANNELID Support
12.6.3.15
DISPC Shadow Mechanism for Registers
12.6.4
MIPI Display Serial Interface (DSI) Controller
12.6.4.1
DSI Block Diagram
12.6.4.2
DSI Clocking
12.6.4.3
DSI Reset
12.6.4.4
DSI Power Management
12.6.4.5
DSI Interrupts
12.6.4.6
DSI Internal Interfaces
12.6.4.6.1
Video Input Interfaces
12.6.4.6.1.1
Pixel Mapping
12.6.4.6.2
DPI (Pixel Stream Interface)
12.6.4.6.2.1
Signals
12.6.4.6.3
SDI (Serial Data Interface)
12.6.4.6.3.1
Secure Display Support
12.6.4.7
DSI Programming Guide
12.6.4.7.1
Application Guidelines
12.6.4.7.1.1
Overview of a Display Subsystem
12.6.4.7.1.2
D-PHY And DSI Configuration
12.6.4.7.1.3
DSI Controller Initialization
12.6.4.7.1.4
Panel Configuration Using Command Mode
12.6.4.7.1.5
VIDEO Interface Configuration
12.6.4.7.2
Application Considerations
12.6.4.7.2.1
D-PHY Timings Control
12.6.4.7.2.2
Control Block
12.6.4.7.2.3
Video Coherency
12.6.4.7.3
Start-up Procedure
12.6.4.7.4
Interrupt Management
12.6.4.7.4.1
Error and Status Registers
12.6.4.7.4.2
Interrupt Management for Direct Command Registers
12.6.4.7.5
Direct Command Usage
12.6.4.7.5.1
Trigger Mapping Information
12.6.4.7.5.2
Command Mode Settings
12.6.4.7.5.3
Bus Turnaround Sequence
12.6.4.7.5.4
Tearing Effect Control
12.6.4.7.5.5
Tearing Effect Control on Panels with Frame Buffer
12.6.4.7.5.6
Return Path Operation
12.6.4.7.5.7
EoT Packet Management
12.6.4.7.5.8
ECC Correction
12.6.4.7.5.9
LP Transmission and BTA
12.6.4.7.6
Low-power Management
12.6.4.7.7
Video Mode Settings
12.6.4.7.7.1
Video Stream Presentation
12.6.4.7.7.2
Video Stream Settings (VSG)
12.6.4.7.7.3
VCA Configuration
12.6.4.7.7.4
TVG Configuration
12.6.4.7.8
DPI To DSI Programming
12.6.4.7.8.1
DSI and DPHY Operation
12.6.4.7.8.2
Pixel Clock to TX_BYTE_CLK Variation
12.6.4.7.8.3
LP Operation
12.6.4.7.8.4
DPI Interface Burst Operation
12.6.4.7.9
Programming the DSITX Controller to Match the Incoming DPI Stream
12.6.4.7.9.1
Vertical Timing
12.6.4.7.9.2
Horizontal Timing for Non-Burst Mode with Sync Pulses
12.6.4.7.9.3
Event Mode Horizontal Timing
12.6.4.7.9.4
Burst Event Mode Horizontal Timing
12.6.4.7.9.5
Burst Mode Operation
12.6.4.7.9.6
Example Configurations
12.6.4.7.9.7
Stereoscopic Video Support
12.6.4.7.10
DSITX Video Stream Variable Refresh
12.6.5
Embedded DisplayPort (еDP) Transmitter
12.6.5.1
EDP Block Diagram
12.6.5.2
EDP Wrapper Functions
12.6.5.2.1
Video Stream Clock/Data Muxing
12.6.5.2.2
Secure Video Content Protection
12.6.5.2.3
DPI_DATA Input Pixel Format Supported
12.6.5.2.4
Audio Input Interface
12.6.5.2.4.1
Audio I2S Signals/Timing
12.6.5.2.4.2
Audio I2S Clock Frequency
12.6.5.3
EDP Transmitter Controller Subsystem (MHDPTX_TOP)
12.6.5.3.1
Display Stream Compression Encoder (DSC)
12.6.5.3.1.1
DSC Encoder Features
12.6.5.3.1.2
Usage Models for EDP
12.6.5.3.2
Display Port Transmitter Controller (MHDPTX Controller)
12.6.5.3.2.1
EDP Transmitter Controller Mode Configurations
12.6.5.4
EDP AUX_PHY Interface
12.6.5.5
EDP Clocks
12.6.5.5.1
Clock Diagram
12.6.5.5.1.1
DPI Interface Clock Sourcing
12.6.5.5.1.2
Memory Clock Gating
12.6.5.5.1.3
PHY Clock Connections
12.6.5.5.2
Clock Groups
12.6.5.6
EDP Resets
12.6.5.7
EDP Interrupt Requests
12.6.5.7.1
EDP_INTR Interrupt Description
12.6.5.7.2
EDP_INTR_ASF Interrupt Description
12.6.5.8
EDP Embedded Memories
12.6.5.8.1
MHDPTX Controller Memories
12.6.5.8.2
DSC Memories
12.6.5.8.3
ECC Aggregation
12.6.5.9
EDP Programmer's Guide
12.6.5.9.1
EDP Controller Programming
12.6.5.9.1.1
MHDPTX Register/Memory Regions
12.6.5.9.1.2
Boot Sequence
12.6.5.9.1.3
Setting Core Clock Frequency
12.6.5.9.1.4
Loading Firmware
12.6.5.9.1.5
FW Running indication
12.6.5.9.1.6
Software Events Handling
12.6.5.9.1.7
DisplayPort Source (TX) Sequence
12.6.5.9.1.8
HDCP
12.6.5.9.1.8.1
Embedded HDCP Crypto
12.6.5.9.1.8.2
Additional Security Features
12.6.5.9.1.8.2.1
KM-Key Encryption
12.6.5.9.1.8.2.2
Cyphertext Stealing
12.6.5.9.1.9
HD Display TX Controller
12.6.5.9.1.9.1
Info-Frame Handling
12.6.5.9.1.9.1.1
EDID Handling
12.6.5.9.1.9.1.2
Audio Control
12.6.5.9.1.9.1.3
Video Control
12.6.5.9.1.10
DPTX TX Controller
12.6.5.9.1.10.1
Protocol over Auxiliary
12.6.5.9.1.10.2
PHY (Physical layer) Handling
12.6.5.9.2
EDP PHY Wrapper Initialization
12.6.5.9.3
EDP PHY Programming
12.7
Camera Subsystem
12.7.1
Camera Streaming Interface Receiver (CSI_RX_IF)
12.7.1.1
CSI_RX_IF Overview
12.7.1.1.1
CSI_RX_IF Features
12.7.1.1.2
CSI_RX_IF Ports
12.7.1.2
CSI_RX_IF Environment
12.7.1.3
CSI_RX_IF Functional Description
12.7.1.3.1
CSI_RX_IF Block Diagram
12.7.1.3.2
CSI_RX_IF Hardware and Software Reset
12.7.1.3.3
CSI_RX_IF Clock Configuration
12.7.1.3.4
CSI_RX_IF Interrupt Events
12.7.1.3.5
CSI_RX_IF Data Memory Organization Details
12.7.1.3.6
CSI_RX_IF PSI_L (DMA) Interface
12.7.1.3.6.1
PSI_L DMA framing
12.7.1.3.6.2
PSI_L DMA error handling due to FIFO overflow
12.7.1.3.7
CSI_RX_IF ECC Protection Support
12.7.1.3.8
CSI_RX_IF Programming Guide
12.7.1.3.8.1
Overview
12.7.1.3.8.2
Controller Configuration
12.7.1.3.8.3
Power on Configuration
12.7.1.3.8.4
Stream Start and Stop
12.7.1.3.8.5
Error Control With Soft Resets
12.7.1.3.8.6
Stream Error Detected – No Error Bypass Mode
12.7.1.3.8.7
Stream Error Detected – Error Bypass Mode
12.7.1.3.8.8
Stream Error Detected – Soft Reset Recovery
12.7.1.3.8.9
Stream Monitor Configuration
12.7.1.3.8.10
Stream Monitor Frame Capture Control
12.7.1.3.8.11
Stream Monitor Timer interrupt
12.7.1.3.8.12
Stream Monitor Line/Byte Counters Interrupt
12.7.1.3.8.13
Example Controller Programming Sequence (Single Stream Operation)
12.7.1.3.8.14
CSI_RX_IF Programming Restrictions
12.7.1.3.8.15
CSI_RX_IF Real-time operating requirements
12.7.2
MIPI D-PHY Receiver (DPHY_RX)
12.7.2.1
DPHY_RX Overview
12.7.2.1.1
DPHY_RX Features
12.7.2.1.2
DPHY_RX Ports
12.7.2.2
DPHY_RX Environment
12.7.2.3
DPHY_RX Functional Description
12.7.2.3.1
DPHY_RX Programming Guide
12.7.2.3.1.1
Overview
12.7.2.3.1.2
Initial Configuration Programming
12.7.2.3.1.2.1
Start-up Sequence Timing Diagram
12.7.2.3.1.3
Common Configuration
12.7.2.3.1.4
Lane Configuration
12.7.2.3.1.5
Procedure: Clock Lane Low Power Analog Receiver Functions Test
12.7.2.3.1.5.1
Description of Procedure
12.7.2.3.1.5.2
Details of the Procedure
12.7.2.3.1.6
Procedure: Data Lane Low Power Analog Receiver Functions Test
12.7.2.3.1.6.1
Description of Procedure
12.7.2.3.1.6.2
Details of the Procedure
12.7.2.3.1.7
Procedure: Clock and Data Lane High Speed Receiver BIST Functions Test
12.7.2.3.1.7.1
Description of Procedure
12.7.2.3.1.7.2
Details of the Procedure
12.7.3
Camera Streaming Interface Transmitter (CSI_TX_IF)
12.7.3.1
CSI_TX_IF Overview
12.7.3.1.1
CSI_TX_IF Ports
12.7.3.2
CSI_TX_IF Features
12.7.3.2.1
CSI_TX_IF Legacy Compatibility
12.7.3.3
CSI_TX_IF Environment
12.7.3.4
CSI_TX_IF Functional Description
12.7.3.4.1
CSI_TX_IF Block Diagram
12.7.3.4.2
CSI_TX_IF Hardware and Software Reset
12.7.3.4.3
CSI_TX_IF Clock Configuration
12.7.3.4.4
CSI_TX_IF Interrupt Events
12.7.3.4.5
CSI_TX_IF Data Memory Organization Details
12.7.3.4.6
CSI_TX_IF PSI_L (DMA) Interface
12.7.3.4.7
CSI_TX_IF ECC Protection Support
12.7.3.5
CSI_TX_IF Programming Guide
12.7.3.5.1
CSI_TX_IF Programming (Configuration Mode)
12.7.3.5.2
CSI_TX_IF System Initialization Programming
12.7.3.5.3
CSI_TX_IF Lane Control Programming
12.7.3.5.4
CSI_TX_IF Virtual Channel and Data Type Management
12.7.3.5.4.1
CSI_TX_IF Data Type Interleaving
12.7.3.5.4.2
CSI_TX_IF Data Type Interleaving with Multiple Interfaces
12.7.3.5.4.3
CSI_TX_IF Virtual Channel Interleaving
12.7.3.5.4.4
CSI_TX_IF Virtual Channel and Data Type Interleaving
12.7.3.5.5
CSI_TX_IF Line Control
12.7.3.5.5.1
CSI_TX_IF Line Control Arbitration
12.7.3.5.6
CSI_TX_IF Lane Manager FSM
12.7.3.5.7
CSI_TX_IF Data Lane Control FSM
12.7.3.5.8
CSI_TX_IF Application Examples
12.7.3.5.8.1
CSI_TX_IF D-PHY Control and Configuration
12.7.3.5.8.2
CSI_TX_IF Clock and Data Lane Enable
12.7.3.5.8.3
CSI_TX_IF DP/DN Signal Swap
12.7.3.5.9
CSI_TX_IF DPHY_TX Status
12.7.3.5.10
CSI_TX_IF ULPS Operation
12.7.3.5.11
CSI_TX_IF System Frame Rate Measurement
12.7.3.5.12
CSI_TX_IF Configuration for PSI_L
12.7.3.5.13
CSI_TX_IF Configuration for Color Bar
12.7.3.5.14
CSI_TX_IF Error Recovery
12.7.3.5.15
CSI_TX_IF Power up/down Sequence
12.8
Shared MIPI D-PHY Transmitter (DPHY_TX)
12.8.1
DPHY_TX Subsystem Overview
12.8.1.1
DPHY_TX Features
12.8.1.2
DPHY_TX Ports
12.8.2
DPHY_TX Environment
12.9
Timer Modules
12.9.1
Global Timebase Counter (GTC)
12.9.1.1
GTC Overview
12.9.1.1.1
GTC Features
12.9.1.1.2
GTC Ports
12.9.1.2
GTC Functional Description
12.9.1.2.1
GTC Block Diagram
12.9.1.2.2
GTC Counter
12.9.1.2.3
GTC Gray Encoder
12.9.1.2.4
GTC Push Event Generation
12.9.1.2.5
GTC Register Partitioning
12.9.2
Windowed Watchdog Timer (WWDT)
12.9.2.1
RTI Overview
12.9.2.1.1
RTI Features
12.9.2.1.2
RTI Not Supported Features
12.9.2.1.3
RTI Ports
12.9.2.2
RTI Functional Description
12.9.2.2.1
RTI Counter Operation
12.9.2.2.2
RTI Digital Watchdog
12.9.2.2.3
RTI Digital Windowed Watchdog
12.9.2.2.4
RTI Low Power Mode Operation
12.9.2.2.5
RTI Debug Mode Behavior
12.9.3
Timers
12.9.3.1
Timers Overview
12.9.3.1.1
Timers Features
12.9.3.1.2
Timers Ports
12.9.3.2
Timers Environment
12.9.3.3
Timers Functional Description
12.9.3.3.1
Timer Block Diagram
12.9.3.3.2
Timer Power Management
12.9.3.3.2.1
Wake-Up Capability
12.9.3.3.3
Timer Software Reset
12.9.3.3.4
Timer Interrupts
12.9.3.3.5
Timer Mode Functionality
12.9.3.3.5.1
1-ms Tick Generation
12.9.3.3.6
Timer Capture Mode Functionality
12.9.3.3.7
Timer Compare Mode Functionality
12.9.3.3.8
Timer Prescaler Functionality
12.9.3.3.9
Timer Pulse-Width Modulation
12.9.3.3.10
Timer Counting Rate
12.9.3.3.11
Timer Under Emulation
12.9.3.3.12
Accessing Timer Registers
12.9.3.3.12.1
Writing to Timer Registers
12.9.3.3.12.1.1
Write Posting Synchronization Mode
12.9.3.3.12.1.2
Write Nonposting Synchronization Mode
12.9.3.3.12.2
Reading From Timer Counter Registers
12.9.3.3.12.2.1
Read Posted
12.9.3.3.12.2.2
Read Non-Posted
12.9.3.3.13
Timer Posted Mode Selection
12.9.3.4
Timers Low-Level Programming Models
12.9.3.4.1
Timer Operational Mode Configuration
12.9.3.4.1.1
Timer Mode
12.9.3.4.1.1.1
Main Sequence – Timer Mode Configuration
12.9.3.4.1.2
Timer Compare Mode
12.9.3.4.1.2.1
Main Sequence – Timer Compare Mode Configuration
12.9.3.4.1.3
Timer Capture Mode
12.9.3.4.1.3.1
Main Sequence – Timer Capture Mode Configuration
12.9.3.4.1.3.2
Subsequence – Initialize Capture Mode
12.9.3.4.1.3.3
Subsequence – Detect Event
12.9.3.4.1.4
Timer PWM Mode
12.9.3.4.1.4.1
Main Sequence – Timer PWM Mode Configuration
12.10
Internal Diagnostics Modules
12.10.1
Dual Clock Comparator (DCC)
12.10.1.1
DCC Overview
12.10.1.1.1
DCC Features
12.10.1.1.2
DCC Ports
12.10.1.2
DCC Functional Description
12.10.1.2.1
DCC Counter Operation
12.10.1.2.2
DCC Low Power Mode Operation
12.10.1.2.3
DCC Suspend Mode Behavior
12.10.1.2.4
DCC Single-Shot Mode
12.10.1.2.5
DCC Continuous mode
12.10.1.2.5.1
DCC Continue on Error
12.10.1.2.5.2
DCC Error Count
12.10.1.2.6
DCC Control and count hand-off across clock domains
12.10.1.2.7
DCC Error Trajectory record
12.10.1.2.7.1
DCC FIFO capturing for Errors
12.10.1.2.7.2
DCC FIFO in continuous capture mode
12.10.1.2.7.3
DCC FIFO Details
12.10.1.2.7.4
DCC FIFO Debug mode behavior
12.10.1.2.8
DCC Count read registers
12.10.2
Error Signaling Module (ESM)
12.10.2.1
ESM Overview
12.10.2.1.1
ESM Features
12.10.2.1.2
ESM Ports
12.10.2.2
ESM Environment
12.10.2.3
ESM Functional Description
12.10.2.3.1
ESM Interrupt Requests
12.10.2.3.1.1
ESM Configuration Error Interrupt
12.10.2.3.1.2
ESM Low Priority Error Interrupt
12.10.2.3.1.2.1
ESM Low Priority Error Level Event
12.10.2.3.1.2.2
ESM Low Priority Error Pulse Event
12.10.2.3.1.3
ESM High Priority Error Interrupt
12.10.2.3.1.3.1
ESM High Priority Error Level Event
12.10.2.3.1.3.2
ESM High Priority Error Pulse Event
12.10.2.3.2
ESM Error Event Inputs
12.10.2.3.3
ESM Error Pin Output
12.10.2.3.4
PWM Mode
12.10.2.3.5
ESM Minimum Time Interval
12.10.2.3.6
ESM Protection for Registers
12.10.2.3.7
ESM Clock Stop
12.10.3
Memory Cyclic Redundancy Check (MCRC) Controller
12.10.3.1
MCRC Overview
12.10.3.1.1
MCRC Features
12.10.3.1.2
MCRC Ports
12.10.3.2
MCRC Functional Description
12.10.3.2.1
MCRC Block Diagram
12.10.3.2.2
MCRC General Operation
12.10.3.2.3
MCRC Modes of Operation
12.10.3.2.3.1
AUTO Mode
12.10.3.2.3.2
Semi-CPU Mode
12.10.3.2.3.3
Full-CPU Mode
12.10.3.2.4
PSA Signature Register
12.10.3.2.5
PSA Sector Signature Register
12.10.3.2.6
CRC Value Register
12.10.3.2.7
Raw Data Register
12.10.3.2.8
Example DMA Controller Setup
12.10.3.2.8.1
AUTO Mode Using Hardware Timer Trigger
12.10.3.2.8.2
AUTO Mode Using Software Trigger
12.10.3.2.8.3
Semi-CPU Mode Using Hardware Timer Trigger
12.10.3.2.9
Pattern Count Register
12.10.3.2.10
Sector Count Register/Current Sector Register
12.10.3.2.11
Interrupts
12.10.3.2.11.1
Compression Complete Interrupt
12.10.3.2.11.2
CRC Fail Interrupt
12.10.3.2.11.3
Overrun Interrupt
12.10.3.2.11.4
Underrun Interrupt
12.10.3.2.11.5
Timeout Interrupt
12.10.3.2.11.6
Interrupt Offset Register
12.10.3.2.11.7
Error Handling
12.10.3.2.12
Power Down Mode
12.10.3.2.13
Emulation
12.10.3.3
MCRC Programming Examples
12.10.3.3.1
Example: Auto Mode Using Time Based Event Triggering
12.10.3.3.1.1
DMA Setup
12.10.3.3.1.2
Timer Setup
12.10.3.3.1.3
CRC Setup
12.10.3.3.2
Example: Auto Mode Without Using Time Based Triggering
12.10.3.3.2.1
DMA Setup
12.10.3.3.2.2
CRC Setup
12.10.3.3.3
Example: Semi-CPU Mode
12.10.3.3.3.1
DMA Setup
12.10.3.3.3.2
Timer Setup
12.10.3.3.3.3
CRC Setup
12.10.3.3.4
Example: Full-CPU Mode
12.10.3.3.4.1
CRC Setup
12.10.4
ECC Aggregator
12.10.4.1
ECC Aggregator Overview
12.10.4.1.1
ECC Aggregator Features
12.10.4.1.2
ECC Aggregator Ports
12.10.4.2
ECC Aggregator Functional Description
12.10.4.2.1
ECC Aggregator Block Diagram
12.10.4.2.2
ECC Aggregator Register Groups
12.10.4.2.3
Read Access to the ECC Control and Status Registers
12.10.4.2.4
Serial Write Operation
12.10.4.2.5
Interrupts
12.10.4.2.6
Inject Only Mode
12.10.4.2.7
ECC Error Injection Sequence
12.10.4.2.7.1
Types of Error Injection
12.10.4.2.7.1.1
ECC Wrapper Type Endpoints
12.10.4.2.7.1.2
EDC Interconnect Type Endpoints
12.10.4.2.7.1.3
Inject Only ECC Endpoints
12.10.4.2.7.1.4
Full Functionality Error Capture ECC Endpoints
12.10.4.2.7.2
Types of ECC Checkers
12.10.4.2.7.2.1
Parity Type Checkers
12.10.4.2.7.2.2
Redundant Type Checkers
12.10.4.2.7.2.3
Error Detect and Correct (EDC) Type Checkers
12.10.4.2.7.3
Recommendations for Testing Error Injection
12.10.4.2.7.4
Error Injection Programming Sequence
12.10.4.2.7.4.1
ESM Initialization
12.10.4.2.7.4.2
ECC Initialization
12.10.4.2.7.4.3
Error Injection
12.10.4.2.7.4.4
Error Handling
12.10.4.3
ECC Aggregator Registers
13
On-Chip Debug
14
Revision History
5.5.26
R5FSS
Instance
WKUP Domain
MCU Domain
Main Domain
MCU_R5FSS[0]
√
R5FSS[1:0]
√