SPRUJ28E November 2021 – September 2024 AM68 , AM68A , TDA4AL-Q1 , TDA4VE-Q1 , TDA4VL-Q1
PLL calibration is intended to reduce a specific form of PLL jitter in which a large correction is present on each reference clock edge. In this case, the calibration logic smooths the correction so that the change to the PLL operation is not as abrupt and therefore it reduces jitter related to the reference clock.
In <PLL_name>_CAL_CTRL register:
Then, set CAL_EN = 1
Wait for <PLL_name>_CAL_STAT[31] CAL_LOCK to be asserted. The CAL_LOCK signal requires a timeout; if the signal is NOT asserted within 2.3ms, the user may continue to use the PLL but should not change CAL_CNT or FAST_CAL (in the next step).
Then, the use may (it is not required):
These optional changes increase the duration for which the calibration solution is measured from 22 + 5 reference clock periods to 27 + 5 reference clock periods.
Calibration cannot be used when the PLL is configured for fractional mode; specifically, this restriction means that PLL_CTRL[1] = 0.