SPRUJ28E November 2021 – September 2024 AM68 , AM68A , TDA4AL-Q1 , TDA4VE-Q1 , TDA4VL-Q1
The HWA0 scheduler in HTS is used for VISS. One example for HTS programming to map VISS on pipeline=0 is as below:
// HWA0 Scheduler Programming (keep default programing for not included parameters)
HTS->HWA0_wdtimer->wdtimer_en = 1; //Activate WD
HTS->HWA0_scheduler_control->pipeline_num = 0; // Belongs to pipeline 0
// HWA0 consumer and producer control
HTS->HWA0_cons_control->cons0_en = 1; // Enable exp-0 Fetch
HTS->HWA0_cons_control->cons1_en = 1; // Enable exp-1 Fetch
HTS->HWA0_cons_control->cons2_en = 1; // Enable exp-2 Fetch
HTS->HWA0_cons_control->prod0_select = 0; // Fixed to UTC
HTS->HWA0_cons_control->prod1_select = 0; // Fixed to UTC
HTS->HWA0_cons_control->prod2_select = 0; // Fixed to UTC
HTS->HWA0_prod0_control->prod_en = 1; // Enable Producer socket
HTS->HWA0_prod0_buf_control->depth = 2; // ping-pong buffer
HTS->HWA0_prod0_control->cons_select = 0; // Fixed to UTC
HTS->HWA0_prod1_control->prod_en = 1; // Enable Producer socket
HTS->HWA0_prod1_buf_control->depth = 2; // ping-pong buffer
HTS->HWA0_prod1_control->cons_select = 0; // Fixed to UTC
HTS->HWA0_prod2_control->prod_en = 1; // Enable Producer socket
HTS->HWA0_prod2_buf_control->depth = 2; // ping-pong buffer
HTS->HWA0_prod2_control->cons_select = 0; // Fixed to UTC
HTS->HWA0_prod3_control->prod_en = 1; // Enable Producer socket
HTS->HWA0_prod3_buf_control->depth = 2; // ping-pong buffer
HTS->HWA0_prod3_control->cons_select = 0; // Fixed to UTC
HTS->HWA0_prod4_control->prod_en = 1; // Enable Producer socket
HTS->HWA0_prod4_buf_control->depth = 2; // ping-pong buffer
HTS->HWA0_prod4_control->cons_select = 0; // Fixed to UTC
HTS->HWA0_prod5_control->prod_en = 1; // Enable Producer socket
HTS->HWA0_prod5_buf_control->depth = 2; // ping-pong buffer
HTS->HWA0_prod5_control->cons_select = 0; // Fixed to UTC
// Exp-0 Fetch
HTS->DMA0_scheduler_control->pipeline_num = 0; // Belongs to pipeline 0
HTS->DMA0_hop->hop = 1; // Head of the pipe scheduler
HTS->DMA0_hop->hop_thread_count = 1080; // Assuming frame height of 1080
HTS->DMA0_scheduler_control->dma_channel_no = 0; // Assign appropriate UDMA channel
HTS->DMA0_prod0_control->prod_en = 1; // Enable producer socket
HTS->DMA0_prod0_buf_control->depth = 2; // ping-pong
HTS->DMA0_prod0_count->count_postload = 23; // Additional triggers for vertical blanking to flush out the VISS.
// Exp-1 Fetch
HTS->DMA1_scheduler_control->pipeline_num = 0; // Belongs to pipeline 0
HTS->DMA1_hop->hop = 1; // Head of the pipe scheduler
HTS->DMA1_hop->hop_thread_count = 1080; // Assuming frame height of 1080
HTS->DMA1_scheduler_control->dma_channel_no = 1; // Assign appropriate DMA channel
HTS->DMA1_prod0_control->prod_en = 1; // Enable producer socket
HTS->DMA1_prod0_buf_control->depth = 2; // ping-pong
HTS->DMA1_prod0_count->count_postload = 23; // Additional triggers for vertical blanking to flush out the VISS.
// Exp-2 Fetch
HTS->DMA2_scheduler_control->pipeline_num = 0; // Belongs to pipeline 0
HTS->DMA2_hop->hop = 1; // Head of the pipe scheduler
HTS->DMA2_hop->hop_thread_count = 1080; // Assuming frame height of 1080
HTS->DMA2_scheduler_control->dma_channel_no = 2; // Assign appropriate DMA channel
HTS->DMA2_prod0_control->prod_en = 1; // Enable producer socket
HTS->DMA2_prod0_buf_control->depth = 2; // ping-pong
HTS->DMA2_prod0_count->count_postload = 23; // Additional triggers for vertical blanking to flush out the VISS.
// VISS output Y-12
HTS->DMA240_scheduler_control->pipeline_num = 0; // Belongs to pipeline 0
HTS->DMA240_scheduler_control->DMA_channel_no = 3; // Assign appropriate DMA channel
HTS->DMA240_cons0_control->cons_en = 1; // Enable consumer socket
// VISS output UV-12
HTS->DMA241_scheduler_control->pipeline_num = 0; // Belongs to pipeline 0
HTS->DMA241_scheduler_control->DMA_channel_no = 4; // Assign appropriate DMA channel
HTS->DMA241_cons0_control->cons_en = 1; // Enable consumer socket
// VISS output Y-8
HTS->DMA242_scheduler_control->pipeline_num = 0; // Belongs to pipeline 0
HTS->DMA242_scheduler_control->DMA_channel_no = 5; // Assign appropriate DMA channel
HTS->DMA242_cons0_control->cons_en = 1; // Enable consumer socket
// VISS output UV-8
HTS->DMA243_scheduler_control->pipeline_num = 0; // Belongs to pipeline 0
HTS->DMA243_scheduler_control->DMA_channel_no = 6; // Assign appropriate DMA channel
HTS->DMA243_cons0_control->cons_en = 1; // Enable consumer socket
// VISS output S-8
HTS->DMA244_scheduler_control->pipeline_num = 0; // Belongs to pipeline 0
HTS->DMA244_scheduler_control->DMA_channel_no = 7; // Assign appropriate DMA channel
HTS->DMA244_cons0_control->cons_en = 1; // Enable consumer socket
// VISS output H3A-AE
HTS->DMA245_scheduler_control->pipeline_num = 0; // Belongs to pipeline 0
HTS->DMA245_scheduler_control->DMA_channel_no = 8; // Assign appropriate DMA channel
HTS->DMA245_cons0_control->cons_en = 1; // Enable consumer socket
// Enable Required Schedulers
HTS->HWA0_scheduler_control->sch_en = 1; //VISS0 Scheduler Enable
HTS->DMA0_scheduler_control->sch_en = 1; //Prod DMA for expo0 Enable
HTS->DMA1_scheduler_control->sch_en = 1; //Prod DMA for expo1 Enable
HTS->DMA1_scheduler_control->sch_en = 1; //Prod DMA for expo2 Enable
HTS->DMA240_scheduler_control->sch_en = 1; //Cons DMA for Y12 Enable
HTS->DMA241_scheduler_control->sch_en = 1; //Cons DMA for UV12 Enable
HTS->DMA242_scheduler_control->sch_en = 1; //Cons DMA for Y8 Enable
HTS->DMA243_scheduler_control->sch_en = 1; //Cons DMA for UV8 Enable
HTS->DMA244_scheduler_control->sch_en = 1; //Cons DMA for S8 Enable
HTS->DMA245_scheduler_control->sch_en = 1; //Cons DMA for H3A Enable
// Enable Pipeline
HTS-> PIPELINE_CONTROL_0 ->pipe_en = 1; // Enable VISS0 pipeline# 0