SPRUJ28E November 2021 – September 2024 AM68 , AM68A , TDA4AL-Q1 , TDA4VE-Q1 , TDA4VL-Q1
This section describes the GPMC0 external connections (environment).
Table 12-161 lists the GPMC subsystem input/output (I/O) pins.
Module Pin | I/O(1) | Description |
---|---|---|
A[27-0] | O | 28-bit output address bus |
A[16-1]/D[15-0] | I/O | Multiplexed address/data |
nCS[3-0] | O | Chip-selects (active low) |
CLK | O | Clock generated for the external memory or device. For more information, see GPMC Integration. |
RET_CLK | ||
N/A | O | Free running clock. GPMC functional clock (GPMC0_FCLK) propagated on a device pad. For more information on the GPMC0_FCLK_MUX integration, see GPMC Integration. |
nADV/ALE | O | Address valid (active low). Also used as address latch enable (active high) for NAND protocol memories. |
nOE/nRE | O | Output enable (active low). Also used as read enable (active low) for NAND protocol memories. |
nWE | O | Write enable (active low) |
nBE0/CLE | O | Lower-byte enable (active low). Also used as command latch enable for NAND protocol memories. |
nBE1 | O | Upper-byte enable (active low) |
WAIT[3-0] | I | External wait signal for NOR and NAND protocol memories. Can be mapped on any of the chip-selects. |
nWP | O | Write protect (active low) |
DIR | O | This signal can be used to control an external buffer direction. Also controls the signal direction of D[15-0]. Low during transmit (for write access: data OUT from GPMC0 to memory). High during receive (for read access: data IN from memory to GPMC0). |