SPRUJ28E November 2021 – September 2024 AM68 , AM68A , TDA4AL-Q1 , TDA4VE-Q1 , TDA4VL-Q1
The timer control module controls the RAM accesses for reading and writing. It controls the loops over the timer RAM, checks the values in the RAM to observe expiring timers, flagging timeouts so that events may be triggered and reported. It also takes as input any software-written updates to setup, clear, and touch the timers.
The timer states are sequential, that is, Timer 0 is checked, then Timer 1 is checked, then Timer 2, and so on. The Timer Control FSM will stall in a given state if the cmd_accept signal from the ksdw_spram_ecc module goes low, and will remain there until the ECC RAM will accept a command.
The timer state always transitions from N to N+1, unless N meets or exceeds the programmed MAX_TIMER value, in which case the system will start over at state 0.