SPRUJ28E November 2021 – September 2024 AM68 , AM68A , TDA4AL-Q1 , TDA4VE-Q1 , TDA4VL-Q1
Each MSMC SRAM bank implements the memory-mapped SRAM snoop filter in its own memory structure similar to a cache tag memory. The snoop filter tracks atomic coherent blocks at the same granularity as the level 3 cache for external memory: 128 bytes.
MSMC also implements a combined snoop filter and level 3 cache for the connected external memory space. As with the memory-mapped SRAM, the snoop filter exists to optimize performance of coherent external memory data cached in the attached level 1 and level 2 coherent caches. The external memory snoop filter is a 32-way set-associative cache structure which tracks coherent data at the same granularity as the SRAM snoop filter: 128 bytes.
SoC and DRU transactions use snoop filter allocation policy which directs allocations strictly into the data-backed portion (ways) of the L3 cache. Random way selection only occurs when the targeted data-backed or non-data-backed portion (ways) of the L3 cache set are fully occupied. This applies also to CPU transactions, if the MSMC_CACHE_CTRL[10] ALLOCATION_POLICY bit is set to 0x0. When the MSMC_CACHE_CTRL[10] ALLOCATION_POLICY bit is set to 0x1, all CPU transactions use a randomized allocation policy which can select between both data-backed and non-data-backed ways.
The level 3 snoop filter/cache randomly chooses a way to replace when allocating a new cache line. The foundation of this random replacement is a 24-bit maximal period Linear Feedback Shift Register (LFSR) tuned to minimize any bias. The state of the LFSR supplies two to five bit allocation pointers depending on the configured cache size/number of ways. Each bank houses its own separately initialized LFSR which updates upon each allocation. For debugging purposes, MSMC supplies a linear mode replacement policy which initializes to the configured number of ways, eventually decrement to zero with allocations, and wrap back around to the total number of ways. Software can enable the linear replacement policy by writing 0x1 to the MSMC_CACHE_CTRL[8] REPLACEMENT_POLICY bit.