SPRUJ28E November 2021 – September 2024 AM68 , AM68A , TDA4AL-Q1 , TDA4VE-Q1 , TDA4VL-Q1
Clocks | |
Module Clock Input | Description |
INTR_AGGR_FICLK | INTR_AGGR clock. This clock is used for all interface and functional operations. |
Resets | |
Module Reset Input | Description |
INTR_AGGR_RST | INTR_AGGR hardware reset |
Interrupt Requests | ||
Module Interrupt Signal | Description | Type |
UDMASS_INTA0_VINTR_PEND[255:0] | Global/local events | Level |
MODSS_INTA0_VINTR_PEND[63:0] | Global events from TIMER_MGR0 | Level |
MODSS_INTA1_VINTR_PEND[63:0] | Global events from TIMER_MGR1 | Level |
L2G Interrupt Request Inputs | ||
Module Interrupt Signal | Description | Type |
L2G_EVENT_PEND[7:0] | Interrupts from TIMESYNC_INTRTR0 | Level |
L2G_EVENT_PEND[15:8] | Interrupts from CMPEVT_INTRTR0 | Level |
L2G_EVENT_PEND[31:16] | Interrupts from GPIOMUX_INTRTR0 | Level |
DMA Events | ||
Module DMA Event | Description | Type |
- | No PDMA channels to external DMA engines | - |