SPRUJ28E November 2021 – September 2024 AM68 , AM68A , TDA4AL-Q1 , TDA4VE-Q1 , TDA4VL-Q1
The PBR logic can be temporarily modified to continuously assert refresh requests. This option may be desirable when the auto-refresh logic is running at a deficit and the user wishes to run per-bank refreshes instead of auto-refreshes to restore the refresh count.
Setting the DDRSS_CTL_71[8] PBR_CONT_REQ_EN bit to 1h enables this mode. Automatic mode falls between the normal priority and high priority commands in terms of priority. When enabled, if the number of all-bank refresh commands pending exceeds the value programmed into the DDRSS_CTL_71[20-16] AREF_PBR_CONT_EN_THRESHOLD field, then the DDR controller automatically begins issuing per-bank refresh commands. As refreshes occur, the pending command count drops. Once that value meets the value programmed in the DDRSS_CTL_71[28-24] AREF_PBR_CONT_DIS_THRESHOLD field, the DDR controller stops automatically issuing per-bank refresh commands.
If however the refresh command pending count exceeds the value programmed into the DDRSS_CTL_227[20-16] AREF_NORM_THRESHOLD field, the DDR controller temporarily suspends the PBR logic, and the auto-refresh logic issues all-bank refresh commands until the refresh logic catches up. Once caught up, the PBR logic is resumed.