The HyperBus module is a high throughput memory interface. It is a part of the device FSS and provides execute in place (XIP) operation and block copy access to HyperBus memory devices (HyperRAM and HyperFlash). The FSS enables in-line ECC protection and authentication features for the HyperBus module.
For more information about FSS, see Flash
Subsystem (FSS).
The HyperBus module is compliant to the Cypress HyperBus™ Specification v1.2.
Figure 12-75 shows the HyperBus module block diagram.
Basic Blocks:
- HBMC: The HyperBus Memory Controller (HBMC) is the main part (the core) of the HyperBus Subsystem and provides accessibility to external HyperBus memory (HyperFlash or HyperRAM) using simple HyperBus protocol for data read and write transfers.
- The Data Port on the HBMC is used for CBASS data slave interface to access the external HyperBus memory.
- The CFG Port on the HBMC is used for configuration of the HBMC registers.
- HyperBus I/O Interface: The HyperBus I/O
Interface includes all used interface pins (for more information, see
HyperBus I/O Signals).
- Memory IF: The Memory IF block implements the following functionality:
- Convert single-rate command and data output from the HBMC to double-rate (DDR)
- Use DLL to delay the incoming read data strobe from the memory
- FIFO Memories with ECC: There are internal HyperBus FIFOs implemented with memories that are used during read and write transactions. These FIFO memories are ECC protected (for more information about the FIFOs, see Section 12.3.3.3.3, HyperBus Internal FIFOs).
- ECC Aggregator: The ECC Aggregator facilitates aggregating and reporting internal HyperBus FIFO memory errors (for more information, see Section 12.3.3.3.2, HyperBus ECC Support).
- HBMC Registers: This block includes set of all used HBMC registers.
- HyperBus Subsystem Registers: This block implements memory-mapped registers at the HyperBus Subsystem level.
- ECC Aggregator Registers: This block includes all
used ECC Aggregator registers.
For more
information about all HyperBus registers, see HyperBus
Registers.
- MCU_CBASS0: The MCU_CBASS0 interconnect implements the clock domain crossing bridges needed to separate the two main clock domains: MCU_CBASS0 clock domain and Memory clock domain.
- Data Slave IF: The Data Slave IF on the interconnect is a 32-bit wide interface and is used to access an external HyperBus memory via the Data Port on the HBMC. The data interface supports linear incrementing addresses only. Cache-line wrap and fixed addressing modes are not supported.
- Config Slave IF: The Config Slave IF on the
interconnect is a 32-bit wide interface and is used to access the HBMC
registers (via the CFG Port on the HBMC), HyperBus Subsystem registers, and
ECC Aggregator registers. The config interface also supports linear
incrementing address mode only.
For more
information about supported and not supported HyperBus features, see
HyperBus Overview.
- Clocks: For more information about HyperBus
Clocks, see MCU_FSS0_HBP0 Clocks and Resets.
- Subsystem Reset: The reset signal to the
Subsystem Reset block provides reset to the all HyperBus Subsystem parts
(for more information about HyperBus Resets, see MCU_FSS0_HBP0 Clocks and
Resets).
- Interrupts: For more information, see
MCU_FSS0_HBP0 Clocks and Resets and HyperBus
Interrupts.