SPRUJ28E November 2021 – September 2024 AM68 , AM68A , TDA4AL-Q1 , TDA4VE-Q1 , TDA4VL-Q1
The BIST engine inside the eMMC PHY leverages the Tuning Pattern to verify the functionality of the PHY (including the IOs and the DLL). The BIST engine is controlled from SOC and the eMMC Host Controller should be disabled during the BIST Mode. The BIST can be run at different modes (Clock Speeds) and the result of the BIST operation is presented to the SOC.
In normal mode, the PHY Transmit Data path operates on the MMCSD0_CLOCK_CONTROL[15:8].SDCLK_FRQSEL. This clock is provided by the eMMC Host Controller and the frequency of this clock is varied based on the operating mode. The following are the various frequencies used in various modes.
This clock is generated by the eMMC Host Controller and under direct control of the software through the Clock Control Register @0x2C of the Host Controller Register Set. The eMMC Host Controller uses the XIN_CLK (the reference clock to the Host Controller, which is usually 200 MHz) and uses the Clock Divider Value and the Clock Enable Control.
The BIST Engine runs on the same MMCSD0_CLOCK_CONTROL[15:8].SDCLK_FRQSEL. Though the Host Controller is disabled during the BIST operation, the software should program the Clock Control Register so that the MMCSD0_CLOCK_CONTROL[15:8].SDCLK_FRQSEL is generated for the BIST engine.