There are four clock domain in the
CSI_TX_IF.
- The CSI_TX_MAIN_CLK(or also
referred to as pixel clock) runs most of the logic. It needs to be same
frequency as CSI_RX_MAIN_CLK main clock (500MHz). When CSI_TX_MAIN_CLK is
operating lower than 312.5MHz, then the clock is essentially limiting the clock
rate of the DPHY_TX. Said another way, CSI_TX_MAIN_CLK must be at least the
DPHY_TXBYTECLKHS rate else FIFOs will overflow, crashing the module.
- The CSI_TX_VBUS_CLK is the
interface configuration clock that runs at half the speed of the CSI_TX_MAIN_CLK
(250MHz).
- The DPHY_TXBYTECLKHS is the clock
supplied by the DPHY_TX PLL and is divided down to byte clock. The DPHY_TX is
designed for max of 10gbps. This translates to a max byte clock of 312.5MHz. The
clock is inactive when DPHY_TX is not in HS operation.
- The CSI_TX_ESC_CLK escape clock
runs at 20MHz. CSI_TX_ESC_CLK is rarely used by the CSI_TX_IF, usually is only
to clock in some low speed control signals from DPHY_TX. The ESC interface is a
low speed DPHY common link to the camera/sensor.
Table 12-403
shows the CSI_TX_IF and DPHY_TX inter-clock dependencies.
Table 12-403 CSI_TX_IF Inter-clock
Dependencies
|
CSI_TX_MAIN_CLK |
CSI_TX_VBUS_CLK |
DPHY_TXBYTECLKHS |
CSI_TX_ESC_CLK |
| Min freq |
DPHY_TXBYTECLKHS freq |
CSI_TX_MAIN_CLK / 2 freq |
N/A |
N/A |
| Max freq |
500MHz |
CSI_TX_MAIN_CLK / 2 freq |
312.5MHz |
20MHz |