SPRUJ28 User guide

SPRUJ28E November 2021 – September 2024 AM68 , AM68A , TDA4AL-Q1 , TDA4VE-Q1 , TDA4VL-Q1

Following are the major groups of clocks in the EDP subsystem:

System clock – This is the VBUSP configuration clock. It is used to source the clock for all internal configuration interfaces (VBUSP and PAB) and the core logic of the MHDPTX controller.
DPI clocks - These are video stream source clocks. These can be sourced either directly from PLL or DSS (that is, DPI_CLK outputs, DSS sourced mode).
PHY I/O clocks - These are clocks used to transmit display port raw data to the SERDES or the clock used to receive audio data from MCASP.

Table 12-378 describes clocks at the EDP boundary.

Table 12-378 EDP Clocks

Clock	Freq Min	Freq Max	Source	Description
EDP_DPTX_CLK	125 MHz	125 MHz	System PLL	Functional clock (all VBUSP/APB/DPTX_core logics are clocked by this clock) Valid Freq: 100 – 200 MHz (125 MHz chosen to be 1/4x of CBASS 500 MHz clock)
EDP_DPI_2_2x_CLK	25 MHz	600 MHz	Video PLL or DSS EDP_DPI_2x_CLK	DPI Streaming Clock – Typically 1x of the corresponding EDP_DPI_2_CLK. But, in DSC split-panel mode, 2x of the EDP_DPI_2_CLK
EDP_DPI_2/3/4/5_CLK	25 MHz	600 MHz	Video PLL or DSS EDP_DPI_CLK	DPI Clock – pixel clock of the EDP_DPI_DATA bus. In DSS-sourced mode, EDP_DPI_n_CLK is the pixel clock of the EDP_DPI_n_DATA bus. In PLL-sourced mode, the pixel clock needs to be internally muxed between EDP_DPI_2_2x_CLK and EDP_DPI_2_CLK depending on the EDP_DPI_DATA type (split panel data or not).
EDP_AIF_I2S_CLK	1 MHz	125 MHz	MCASP	Audio I2S Clock (192 kHz clock)
PHY_LN0_TXMCLK (SOURCE_PHY_DATA_CLK)	81 MHz	405 MHz	DP-SERDES (PHY) PLL	PHY Data clock (1/2 Char Clock)
PHY_LN0_TXFCLK (SOURCE_PHY_CHAR_CLK)	162 MHz	810 MHz	DP-SERDES (PHY) PLL	PHY Char Clock