SPRUJ28E November 2021 – September 2024 AM68 , AM68A , TDA4AL-Q1 , TDA4VE-Q1 , TDA4VL-Q1
When a processing thread is only performing an octave generation (1/2x single phase resizing), the next input lines can be offset by 2 lines since the output is only generated every other input line times. By skipping lines (VPAC_MSC_LSE_SRC_CFG_j[7] SRC_LN_INC_2), the SL2 access is reduced in half for this mode and the cycle time to complete an Octave generation is equal to ½ of the input frame size.
Line N: Read Line N-2, N-1, N, N+1, N+2
Line N+1: Skip
Line N+2: Read Line N, N+1, N+2, N+3, N+4
Line N+3: Skip
Even though “N+1” line processing is skipped, all source lines are still required for proper filtering. Therefore, the DMA transfer from DDR to SL2 should include all lines. VPAC_MSC_CORE_FIRINC_j[30-16] VS should be set to 4096 (1x resizing) to compensate for source line skip (if it is doing a ½ resizing).
Horizontal Skip is done normally as ½ x resizing by the core HScale Filter.