Follow the procedure described in section Section 12.7.2.3.1.2, but do not release the common or lanes from reset.
Write the following registers.
PMA Register (cmn): DPHY_RX_VBUS2APB_CMN0_CMN_DIG_TBIT21[0] O_RX_DIG_BIST_EN =
1’b1, to enable the analog BIST power island in common.
PMA Register (clock lanes): DPHY_RX_VBUS2APB_DL0_RX_DIG_TBIT2 -
DPHY_RX_VBUS2APB_DL3_RX_DIG_TBIT2 [24] = 1’b1, to enable the
diagnostic low power override MUXes in the analog.
PMA Register (clock lanes): DPHY_RX_VBUS2APB_DL0_RX_DIG_TBIT2 -
DPHY_RX_VBUS2APB_DL3_RX_DIG_TBIT2 [21:20] = 2’b11, to enable the
diagnostic high speed override MUXes in the analog.
PMA Register (data lanes): DPHY_RX_VBUS2APB_DL0_RX_DIG_TBIT30 -
DPHY_RX_VBUS2APB_DL3_RX_DIG_TBIT30[1:0] = 2’b11, to enable the
diagnostic low power and high speed override MUXes in the
analog.
Release the common from reset, and wait for
DPHY_RX_VBUS2APB_ISO_PHY_ISO_CMN_CTRL[5] O_CMN_READY to be driven to
1’b1.
Release the clock and data lanes from reset, and wait for
DPHY_RX_VBUS2APB_ISO_PHY_ISO_CMN_CTRL[8] LANE_READY_CMN to be driven to
1’b1.
Poll PMA Register (cmn): DPHY_RX_VBUS2APB_CMN0_CMN_DIG_TBIT56[20-11]
I_CMN_RX_SSM_STATE until it is set to 9’b100000000.
When running BIST at 1.5 Gbps, do the following, otherwise skip this if running BIST at 2.5 Gbps.
At this point, the BIST generator and checker registers can be written to the values required to generate the desired data patterns. One should see the BIST register descriptions for information about programming the various fields for creating different data patterns. If no registers are written, the BIST default pattern will be generated and checked.
If running infinite BIST mode is desired, write the PMA Register (cmn):
DPHY_RX_VBUS2APB_CMN0_CMN_DIG_TBIT24[15] BIST_INF_MODE = 1’b1, to enable
infinite BIST mode.
Write PMA Register (data lanes): DPHY_RX_VBUS2APB_DL0_RX_DIG_TBIT27[0] = 1’b1,
to enable the pattern checkers in the data lanes.
Write PMA Register (cmn): CMN_DIG_TBIT22[0] TM_BIST_EN = 1’b1, to enable the pattern generator in the common.
If infinite BIST mode was enabled, do the following.
Allow the BIST to run as long as required.
Write the PMA Register (cmn lanes): DPHY_RX_VBUS2APB_CMN0_CMN_DIG_TBIT24[15]
BIST_INF_MODE = 1’b0, to disable infinite BIST mode.
Wait for a minimum of 100 nSec.
Poll PMA Register (cmn): DPHY_RX_VBUS2APB_CMN0_CMN_DIG_TBIT50[1] BIST_COMPLETE
until it is set to 1’b1, indicating that the BIST pattern generation process is
complete.
Wait 1 uSec.
Read and confirm the PMA Register (data lanes):
DPHY_RX_VBUS2APB_DL0_RX_DIG_TBIT48 - DPHY_RX_VBUS2APB_DL3_RX_DIG_TBIT48[0]
W_DRX_BIST_PASS = 1’b1, indicating the BIST checker has indicated a pass
condition.
Read and confirm the PMA Register (data lanes):
DPHY_RX_VBUS2APB_DL0_RX_DIG_TBIT48 - DPHY_RX_VBUS2APB_DL3_RX_DIG_TBIT48[1]
R_PAT_CHE_SYNC = 1’b1, indicating the BIST checker has observed a marker
symbol.
Read and confirm the PMA Register (data lanes):
DPHY_RX_VBUS2APB_DL0_RX_DIG_TBIT48 - DPHY_RX_VBUS2APB_DL3_RX_DIG_TBIT48[2]
W_BIST_ERROR = 1’b0, indicating the BIST checker has not detected any
errors.
Read and confirm the PMA Register (data lanes):
DPHY_RX_VBUS2APB_DL0_RX_DIG_TBIT47 - DPHY_RX_VBUS2APB_DL3_RX_DIG_TBIT47[15:0]
W_PAT_CHE_PKT_COUNT = the generated number of packets (15 by default).
Read and confirm the PMA Register (data lanes):
DPHY_RX_VBUS2APB_DL0_RX_DIG_TBIT47 - DPHY_RX_VBUS2APB_DL3_RX_DIG_TBIT47[31:16]
W_PAT_CHE_ERROR_COUNT = 16’h0000, indicating the BIST checker error count is
0.
Clear the internal state of the BIST pattern checkers by doing the following:
Write PMA Register (data lanes): DPHY_RX_VBUS2APB_DL0_RX_DIG_TBIT29 -
DPHY_RX_VBUS2APB_DL3_RX_DIG_TBIT29[28] TM_CLEAR_BIST = inverted value of
what was read from this bit in the previous step.
Write PMA Register (data lanes): DPHY_RX_VBUS2APB_DL0_RX_DIG_TBIT27 -
DPHY_RX_VBUS2APB_DL3_RX_DIG_TBIT27[0] TM_BIST_EN = 1’b0, to disable the pattern
checkers in the data lanes.
Clear the internal state of the BIST pattern generator by doing the following:
Write the PMA Register (cmn): DPHY_RX_VBUS2APB_CMN0_CMN_DIG_TBIT24[6] =
1’b1,
Write the PMA Register (cmn): CMN_DIG_TBIT24[6] BIST_CLEAR = 1’b0.
Write the PMA Register (cmn): DPHY_RX_VBUS2APB_CMN0_CMN_DIG_TBIT22[0]
BIST_CONTROLLER_EN = 1’b0, to disable the BIST pattern generator.
If desired, the run BIST operations can be repeated without needing to run set up the IP for BIST operations again.