SPRUJ28E November 2021 – September 2024 AM68 , AM68A , TDA4AL-Q1 , TDA4VE-Q1 , TDA4VL-Q1
Configuration Register / Pin | Configuration Requirement |
---|---|
PHY Pin: psm_clock_freq PHY Register: DPHY_RX_VBUS2APB_PCS_TX_DIG_TBIT1 | Set the PMA state machine clock frequency divider. Set either the pin or the register, as specified in the respective description, for the required PMA state machine clock. |
PHY Pin: ipconfig_cmn PHY Register: DPHY_RX_MMR_SLV_LANE[11-9] IPCONFIG_CMN | Set the clock lane configuration. Set as specified in the description for the required clock lane configuration. |
PMA Register: DPHY_RX_VBUS2APB_CMN0_CMN_DIG_TBIT2[0] O_CMN_SSM_EN, DPHY_RX_VBUS2APB_CMN0_CMN_DIG_TBIT2[10] O_CMN_RX_MODE_EN | Enable the startup state machines for TX mode of operation. Set both register bits to 1’b1. |
PMA Register: DPHY_RX_VBUS2APB_CMN0_CMN_DIG_TBIT35 | Set the RX oscillator calibration feedback clock counter start values. Set the register fields, as specified in the description for the required PMA state machine clock and oscillator clock. |
PHY Register: DPHY_RX_VBUS2APB_PCS_TX_DIG_TBIT2 | Set the required power island phase 2 time. Set the register to 32’hAAAAAAAA. |
PHY Register: DPHY_RX_VBUS2APB_PCS_TX_DIG_TBIT3[7:4] POWER_SW_2_TIME_CL_R, DPHY_RX_VBUS2APB_PCS_TX_DIG_TBIT3[3:0] POWER_SW_2_TIME_CL_L | Set the required power island phase 2 time. Set the register to 8’hAA |