SPRUJ28E November 2021 – September 2024 AM68 , AM68A , TDA4AL-Q1 , TDA4VE-Q1 , TDA4VL-Q1
This is the HS200 mode where the eMMC CLK is set to 200 MHz. To emulate the Interface timing, a small Hold time is inserted on Transmit data lines by using the Phase shifted TX Clock. The amount of phase shift can be from 1 to 16 Taps. The RxClock Phase is adjusted from 1 to 32 Phases to check the data at different phases. In this mode, the TX Phase shift is being performed by using one of the first 16-taps of the DLL TXCLK Phases and the RX Phase shift is being performed by using one of the 32 taps of the DLL RXCLK Phases.