SPRUJ28E November 2021 – September 2024 AM68 , AM68A , TDA4AL-Q1 , TDA4VE-Q1 , TDA4VL-Q1
The device level requirement is to align frame syncs across McASP that may be feeding DACs with different formats but the same frequency.
The intent of is to provide a mechanism to check for the alignment of frame syncs. This works by feeding the frame sync of McASP into the a receive data pin of McASP. If this serializer is enabled as a receiver, then the frame sync of McASP will appear as receive data for McASP.
To adjust the McASP transmit bit clock, the MCASP_ACLKXCTL[17-16] CLKXADJ register bit field can be used to lengthen (write 0x2) or reduce (write 0x1) the McASP bit clock period in a one-shot fashion. After each adjustment the frame sync should be checked again and the process repeated until the two frame syncs are aligned.
This process is expected to be carried out once, before any audio transfers occur. It is not intended to be used for sample rate conversion but rather initial phase alignment of transmit data across McASP.