SPRUJ28E November 2021 – September 2024 AM68 , AM68A , TDA4AL-Q1 , TDA4VE-Q1 , TDA4VL-Q1
Timer Resolution
The Timer resolution and interrupt period are dependent on the selected input clock and clock prescale value. Example resolutions for common clock values are shown in Table 5-60.
Clock | Prescaler | Resolution | Interrupt Period Range |
---|---|---|---|
32.768 KHz | 1 (min) | 31.25 µs | 31.25 µs to ͂36 hr, 35 mins |
256 (max) | 8 ms | 8 ms to ͂391 days, 22 hr, 48 mins | |
27 MHz | 1 (min) | ͂42 ms | ͂42 ms to ͂179 sec |
256 (max) | ͂10.67 µs | ͂10.67 µs to ͂12 hr, 44 mins |
Timer Cascading
Each odd numbered Timer instance within the MCU Domain may be optionally cascaded with the previous even numbered Timer instance to form an up to 64-bit timer.
Each odd numbered Timer instance within the MAIN Domain may be optionally cascaded with the previous even numbered Timer instance to form an up to 64-bit timer.
DMTIMER1 may be cascaded to DMTIMER0
DMTIMER3 may be cascaded to DMTIMER2
...
DMTIMER19 may be cascaded to DMTIMER18
When cascaded, MCU_DMTIMERn acts as a 32-bit prescaler to MCU_DMTIMER[n+1]. The MCU_DMTIMERn must be configured to generate a PWM output edge at the desired rate to increment the MCU DMTIMER[n+1] counter. The same cascading rules apply for MAIN Domain DMTIMERs.
Timer IO Multiplexing
The Device provides 10 MCU_TIMERIO pins and 8 TIMERIO pins to be used as Timer Capture inputs or as Timer PWM outputs. In order to provide maximum flexibility, the 10 MCU_TIMERIO pins may be used with any of the 10 MCU_DMTIMER[9:0] instances, and the 8 TIMERIO pins may be used with any of the 20 DMTIMER[19:0] instances. System-level muxes configured in the CTRL_MMRs are used to control the capture source pin and PWM ouptut source for each MCU_DMTIMER and DMTIMER instance.